CLC411AMC datasheet(5/8 Pages) NSC

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Figure 5C: ECL Interface

Figure 5B: Differential ECL Interface

Figure 5A: Disable Interface

+15V

-15V

3.57k

Ω

Disable

CLC411 pin 8, DISABLE

330

Ω

-5.2V

ECL

Gate

-5.2V

330

Ω

Q1,Q2 MPSH10

Q3,Q4 MPSH81

0.1

µF

0.1

µF

0.1

µF

-15V

-5.2V

10k

Ω

330

Ω

931

Ω

ECL

Gate

0.1

µF

1N914

332

Ω

TTL

Gate

Ω

non-zero Rf must be used with current-feedback

operational amplifiers such as the CLC411. Application

note OA-13, “Current-Feedback Loop-Gain Analysis

and Performance Enhancements,” explains the

ramifications of Rf and how to use it to tailor the desired

frequency response with respect to gain. The equations

found in the application note should be considered as a

starting point for the selection of Rf. The equations do

not factor in the effects of parasitic capacitance found

on the inverting input, the output nor across the feedback

resistor. Equations in OA-13 require values for Rf

(301

Ω), Av (+2) and R

i (inverting input resistance, 50

Ω).

Combining these values yields a Zt* (optimum feedback

transimpedance) of 400

Ω. Figure 4 entitled

"Recommended Rf vs. Gain" will enable the selection of

the feedback resistor that provides a maximally flat

frequency response for the CLC411 over its gain range.

The linear portion of the two curves (i.e. AV>4) results

from the limitation on Rg (i.e. Rg

≥50Ω).

Enable/Disable Operation

The disable feature allows the outputs of several CLC411

devices to be connected onto a common analog bus

forming a high-speed analog multiplexer. When disabled,

the output and inverting inputs of the CLC411 become

high impedances. The disable pin has an internal pull-

up resistor which is pulled-up to an internal voltage, not

to the external supply. The CLC411 is enabled when pin

8 is left open or pulled-up to

≥+7V and disabled when

grounded or pulled below +3V. CMOS logic devices are

necessary to drive the disable pin. For example, CMOS

logic with VDD

≥ +7V will guarantee proper operation over

temperature. TTL voltage levels are inadequate for

controlling the disable feature.

For faster enable/disable operation than 15V CMOS

logic devices will allow, the circuit of Figure 5 is

recommended. A fast four-transistor comparator, Figure

5A, interfaces between the CLC411 DISABLE pin and

several standard logic families.

This circuit has a

differential input between the bases of Q1 and Q2. As

such it may be driven directly from differential ECL

logic, as in shown in Figure 5B. Single-ended logic

families may also be used by establishing an appropriate

threshold voltage on the Vth input, the base of Q2.

Figures 5C and 5D illustrate a single-ended ECL and

TTL interface respectively. The Disable input, the base

of Q1, is driven above and below the threshold, Vth.

Fastest switching speeds result when the differential

voltage between the bases of Q1 and Q2 is kept to less

CLC411

DIS (pin 8)

Buffers

DIS (pin 8)

Figure 6: General Multiplexing Circuit

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Figure 5D: TTL Interface

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