CLC405 datasheet(4/6 Pages) NSC

4 / 6 page

CLC405 Typical Performance Characteristics (A

V = +2, Rf = 348Ω:Vcc = + 5V, RL = 100Ω unless specified)

IBI, IBN, VIO vs. Temperature

-60

-20

140

Temperature (oC)

VIO

4.0

3.0

2.0

1.0

-1.0

1.0

-1.0

-2.0

-3.0

-4.0

100

IBI

IBN

CLC405 OPERATION

Feedback Resistor

The feedback resistor, Rf, determines the loop gain and

frequency response for a current feedback amplifier.

Unless otherwise stated, the performance plots and data

sheet specify CLC405 operation with Rf of 348Ω at a

gain of +2V/V. Optimize frequency response for different

gains by changing Rf. Decrease Rf to peak frequency

response and extend bandwidth. Increase Rf to roll off

of the frequency response and decrease bandwidth. Use

a 2k

Ω R

f for unity gain, voltage follower circuits.

Use application note OA-13 to optimize your Rf selec-

tion. The equations in this note are a good starting

point for selecting Rf. The value for the inverting input

impedance for OA-13 is approximately 182

Ω.

Enable/Disable Operation Using ± 5V Supplies

The CLC405 has a TTL & CMOS logic compatible

disable function.

Apply a logic low (i.e. < 0.8V) to pin

8, and the CLC405 is guaranteed disabled across its

temperature range. Apply a logic high to pin 8, (i.e. >

2.0V) and the CLC405 is guaranteed enabled. Voltage,

not current, at

pin 8 determines the enable/disable

state of the CLC405.

Disable the CLC405 and its inputs and output become

high impedances. While disabled, the CLC405’s

quiescent power drops to 8mW.

Use the CLC405’s disable to create analog switches or

multiplexers. Implement a single analog switch with one

CLC405 positioned between an input and output.

Create an analog multiplexer with several CLC405s.

Tie the outputs together and put a different signal on

each CLC405 input.

Operate the CLC405 without connecting pin 8.

internal 20k

Ω pull-up resistor guarantees the CLC405

is enabled when pin 8 is floating.

Enable/Disable Operation for Single or

Unbalanced Supply Operation

Figure 1

Figure 1 illustrates the internal enable/disable opera-

tion of the CLC405. When pin 8 is left floating or is tied

to +Vcc, Q1 is on and pulls tail current through the

CLC405 bias circuitry.

When pin 8 is less than

0.8V above the supply midpoint, Q1 stops tail current

from flowing in the CLC405 circuitry. The CLC405 is

now disabled.

Disable Limitations

The feedback resistor, Rf, limits off isolation in inverting

gain configurations. Do not apply voltages greater than

+Vcc or less than -Vee to pin 8 or any other pin.

Small Signal Pulse Response

Time (5ns/div)

0.20

0.10

-0.10

-0.20

0.00

AV-1

AV+1

Large Signal Pulse Response

Time (5ns/div)

2.0

1.0

-1.0

-2.0

0.0

AV-2

AV+2

Settling Time vs. Capacitive Load

100

1000

CL (pF)

348

Ω

348

Ω

o = 2V step

CLC405

100

Short Term Settling Time

Time (ns)

0.2

0.1

-0.1

-0.2

0.0

020

100

Vout = 2Vstep

PSRR and CMRR

10k

100k

Frequency (Hz)

10M

100M

PSRR

CMRR

20k

Ω

20k

Ω

Pin 8

Disable

Pin 4

-Vee

20k

Ω

Bias

Circuitry

I Tail

Supply

Mid-Point

Pull-up

Resistor

Pin 7

+Vcc

CLC405

NOTE: Pins 4, 7, 8 are external

Vcc -Vee

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