LTC4240IGN datasheet(16/28 Pages) LINER

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LTC4240

4240f

A high to low transition on BD_SEL# causes the voltages

on the TIMER, GATE, 3VOUT, 5VOUT, 12VOUT and VEEOUT

pins to begin ramping (see Figure 4). The TIMER pin

capacitance is charged by an 11.5

µA current source while

the GATE capacitance is charged by a 65

µAcurrentsource.

Concurrently, an internal charge pump turns on the gates

of the internal power switches that isolate the 12V and

–12V supplies. All faults are ignored during the time that

the voltage at the TIMER pin remains below 5.5V. In order

to avoid faults due to the charging of the bulk output

capacitors, all output voltages must settle before the

TIMER pin reaches 5.5V. See TIMER section for more

details.

The 5VOUT and 3VOUT supply outputs will ramp up accord-

ing to the slowest of the following slew rates:

LIMIT V

LOAD V

LOAD VOUT

LIMIT V

LOAD V

LOAD VOUT

= µ

–

,( )

–

()

stage in the hot plug sequence, indicating that the

LTC4240 is in reset mode with all power switches off

(BD_SEL# is still pulled high to long 5V).

The 12V and –12V supplies make contact at this stage.

Zener clamps Z1 and Z2 plus shunt RC snubbers R13-

C4 and R14-C5 help protect the 12VIN and VEEIN pins,

respectively, from large transient voltages during hot

insertion and short-circuit conditions.

The signal pins also connect at this point. This includes

the HEALTHY# signal connecting to the PWRGD pin

and the PCI_RST# signal connecting to the RESETIN

pin. The PWRGD and RESETIN signals are combined

internally with Bit 3 (C3) of the I2C command latch (see

Send Byte protocol) to generate the LOCAL_PCI_RST#

signal, which is available at the RESETOUT pin.

4. Short pins make contact. BD_SEL# signal connects to

the OFF/ON pin. This starts the electrical part of the

connection process. If the BD_SEL# signal is grounded

on the backplane, then the electrical connection pro-

cess starts immediately. Note that the electrical con-

nection process can be interrupted with the Send Byte

protocol of the I2C serial interface.

System backplanes that do not ground the BD_SEL#

signal will instead have circuitry that detects when

BD_SEL# has made contact with the plug-in board. The

backplane logic can then control the power up process

by pulling BD_SEL# low. Figure 4 illustrates the power

up sequence. The mating of BD_SEL# is represented by

the high to low transition of the BD_SEL# signal.

Power-Up Sequence

Two external N-channel power MOSFETs isolate the 3.3V

and 5V power paths, while two internal MOS switches

isolate the 12V and –12V power paths. (See front page

Application Circuit). Sense resistors R1 and R2 provide

current limit and fault detection for the 3VIN and 5VIN

supplies, while R5 and C1 provide current control loop

compensation. Current fault detection for the 12V and

–12V supplies is done internally.

TIMER

10V/DIV

GATE

10V/DIV

12VOUT

10V/DIV

VEEOUT

10V/DIV

5VOUT

10V/DIV

3VOUT

10V/DIV

LCL_PCI_RST#

5V/DIV

BD_SEL#

5V/DIV

HEALTHY#

5V/DIV

10ms/DIV

4240 F04

Figure 4. Normal Power-Up Sequence

APPLICATIO S I FOR ATIO

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