The Test Out output is intended for monitoring by equipment

Ω). If the Lock

Detect output is to be externally monitored, the attached

monitoring circuit should present a DC resistance greater

than 5 k

Ω so as not to affect Lock Detect indicator operation.

MEASURING JITTER

The test method used to obtain the timing jitter value given in

the AC Electrical Specification table is based on procedures

and equipment described in SMPTE RP 192-1996. The rec-

ommended practice discusses several methods and indica-

tor devices. An FFT method performed by standard video

test equipment was used to obtain the data given in this data

sheet. As such, the jitter characteristics (or jitter floor) of the

measurement equipment, particularly the measurement ana-

lyzer, become integral to the resulting jitter value. The

method and equipment were chosen so that the test can be

easily duplicated by the design engineer using most stan-

dard digital video test equipment. In so doing, similar results

should be achieved. The intrinsic jitter floor of the CLC021’s

PLL is approximately 25% of the typical jitter given in the

electrical specifications. In production, device jitter is mea-

sured on automatic IC test equipment (ATE) using a different

method compatible with that equipment. Jitter measured

using this ATE yields values approximately 50% of those

obtained using the video test equipment.

10136809

Connect LOCK DETECT to TPG ENABLE for test pattern generator function.

Remove RP1 & RP3 and replace RP2 & RP4 with 50

Ω resistor packs for coax interfacing.

Install RP1-4 when using ribbon cable for input interfacing.

This board is designed for use with TTL power supplies only.

FIGURE 9. SD021EVK Schematic Diagram

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