CALCULATING THE POWER DISSIPATION IN AN

EXPANDED ARRAY

The CLC016 dissipates about 100 mW per active output plus

about 50 mW quiescent power. With all outputs active, this is

about 850 mW. In an expanded array, all devices will dissi-

pate quiescent power, but only those devices with active out-

puts will dissipate the 100 mW/output. So, an N-by-M device

array (an 8xN-input-by-8xM-output switch) with all outputs

active will dissipateNxMx50mW+8xMx100 mW. A 32-

input x 32-output (4 x 4 device) switch array dissipates4x4

x50mW+8x4x100 mW=4W.

CONTROLLED IMPEDANCE TRANSMISSION LINES

AND OTHER LAYOUT TECHNIQUES

length of the highest frequencies present in the transmitted

signal require proper attention to impedance control to avoid

distortion of the signal. Digital signals are especially suscep-

tible to distortion due to poorly controlled line characteristics

and reflections. With its 250 ps output transitions, which im-

ply a bandwidth of 4 GHz or more, transmission lines driven

by the CLC018 must be carefully designed and correctly ter-

minated. Either microstrip line, which resides on the outer

surfaces of a printed circuit board and paired with an image

ground plane, or stripline, which is sandwiched in an inner

layer between image ground planes, may be used in

CLC018 designs. With either line type, it is important to

maintain a uniform characteristic impedance over the entire

extent of the transmission line system. Likewise, the receiv-

ing end of these lines must be terminated in a resistance

equal to the characteristic impedance to preserve signal fi-

delity.

Figure 13 shows representative methods of interfacing

to and from the CLC018.

Often, when voltage-mode drivers, such as ECL, with low

output impedance (also called equivalent generator resis-

tance) are used to drive bus networks, a series resistor con-

nects the output of the amplifier to the transmission line. This

resistor serves both as a termination for any signals travel-

ling toward the source- end of the line and as the series leg

of a voltage divider (with the transmission line as the shunt

leg) to reduce the transmitted signal level. This resistor’s cor-

rect value is Z

be used successfully in most situations. The receiving end of

the line is terminated in a resistance equal to the value of Z

O

of the receiving end of the line. A resistance equal to the

line’s Z

heavily loaded, the receiving end termination’s value may

need to be reduced to the loaded- Z

the material on distributed loading effects on line character-

istics in the

Fairchild F100K ECL 300 Series Databook and

Design Guide).

Current-mode drivers, with their high equivalent generator

resistance, when used as bus drivers require a resistance

equal to Z

as appropriate for the design.

A detailed discussion of digital transmission line design tech-

niques is beyond the scope of this data sheet, but many

good references are available from National Semiconductor

and others. Extensive material is available in the

National In-

terface Databook, the Fairchild F100K ECL 300 Series Da-

tabook and Design Guide and the Motorola MECL System

Design Handbook.

Especially useful is the National Semiconductor

Transmis-

sion Line RAPIDESIGNERr Sliderule and user manual AN-

905. The RAPIDESIGNER is available by calling the Na-

tional Semiconductor Customer Response Center in your

area and asking for either Literature Number 633200-001

(ISO Metric units) or 633201-001 (English units). The User

Manual for both versions is Literature Number 100905-002

and is available on our WEB Site at http://www.national.com

as

AN-905.

www.national.com

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