CLC016ACQ datasheet(15/20 Pages) NSC

15 / 20 page

Product Description (Continued)

CONTROL LINE INTERFACES

The use of the CLC016 with +5V supplies allows the control

lines to interface to standard TTL logic signals. Operating the

CLC016 at −5.2V requires level-shifting circuits for the con-

trol line inputs. Refer to the

Static Performance section of

the

Electrical Characteristics page for required input volt-

age levels.

POWER CONSUMPTION

The power supply current given in the Electrical Characteris-

tics table includes the current required for both the clock and

data output buffers to drive a 75

Ω load to ECL swings.

TYPICAL APPLICATIONS

The CLC016 was designed as one of a series of data trans-

mission support chips. The CLC016 is recommended for a

wide variety of clock and data recovery applications that fit

within its range of data rates.

Serial Data Transmission over Cable

Serial data transmission is common for all types of commu-

nication channels where the data is sent over coaxial or

twisted pair cable.

Figure 21 shows a typical connection us-

ing a CLC006 driver chip, CLC014 Adaptive Cable Equalizer,

and the CLC016 Data Retiming PLL. The CLC016 extracts

the clock and retimes the data from the serial bit stream.

The components recommended in

Figure 21 support the

four common data rates specified in SMPTE 259M.

ESD

The CLC016 is a

CMOS chip. Operators are cautioned to

use grounding straps when handling.

MEASUREMENTS & EVALUATION

When evaluating the CLC016 Data Retimer, it is recom-

mended that you solder the part to the board or use a lead-

less chip carrier socket. Probing with capacitive probes will

disturb the CLC016 performance. When probing the signal

levels use a

1 pF capacitance probe with a 500

Ω tip.

The block diagram below shows a simple method of measur-

ing the clock to eye pattern jitter. Use of the CLC016 evalu-

ation board is recommended for jitter evaluation. It also pro-

vides a good reference for a user’s circuit board design. The

plot in

Figure 23 shows a histogram of the jitter and where

the measurements were taken.

DS100087-32

FIGURE 20. Load Terminated Output Interface

DS100087-33

FIGURE 21. Typical Cable Connection

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