OUTPUT INTERFACING

The CLC006’s class AB output stage,

Figure 6, requires no

standing current in the output transistors and therefore re-

quires no biasing or pull-down resistors. Advantages of this

arrangement are lower power dissipation and fewer external

components. The output may be either D.C. or A.C. coupled

to the load. A bandgap voltage reference sets output voltage

levels which are compatible with F100K and 10K ECL when

correctly terminated. The outputs do not have the same out-

put voltage temperature coefficient as 10K. Therefore, noise

margins will be reduced over the full temperature range

when driving 10K ECL. Noise margins will not be affected

when interfacing to F100K since F100K is fully voltage and

temperature compensated.

DS100084-6

FIGURE 3. DC Coupled Input

DS100084-7

FIGURE 4. Single Ended 50

Ω ECL Input

DS100084-8

FIGURE 5. Differential 50

Ω ECL Input

DS100084-9

FIGURE 6. Output Stage

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