ADAV4601BSTZ datasheet(43/60 Pages) AD

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ADAV4601

Rev. B | Page 43 of 60

Address 0x0118 Headphone 1/AUXOUT4 Seven Band EQ Control Register (Default: 0x0018)

Table 34.

Bit No.

Bit Name

Description

Default

Bits[15:11]

Reserved

Always write as 0 if writing to this register.

00000

Bits[10:8]

Headphone 1/

AUXOUT4 EQ band

These register bits control the frequency band of the equalizer.

000

0x0 = 120 Hz

0x1 = 200 Hz

0x2 = 500 Hz

0x3 = 1200 Hz

0x4 = 3000 Hz

0x5 = 7500 Hz

0x6 = 12000 Hz

Bits[7:6]

Reserved

Always write as 0 if writing to this register.

Bits[5:0]

Headphone 1/

AUXOUT4 EQ gain

These register bits are used to control the required gain of the equalizer. The gain of the

equalizer is changed in 0.5 dB steps.

001110

0x00 = +12 dB

0x01 = +11.5 dB

…

0x0A = +7 dB

…

0x18 = 0 dB

…

0x26 = −7 dB

…

0x2F = −11.5 dB

0x30 = −12 dB

Address 0x011A and Address 0x011B Headphone 1/AUXOUT4 Left Balance Control Registers (Default: 0x0080, 0x0000)

These two registers control the balance for the Left Headphone 1 and AUXOUT 4 output.

The balance control words are 28-bit words in twos complement and a 5.23 format. This means there are five bits to the left of the decimal

point of which the most significant bit is the sign bit.

Table 35.

Bit No.

Bit Name

Description

Default

Bits[15:12]

Reserved

Always write as 0 if writing to this register.

0000

Bits[11:0]

Woofer left balance

control register[27:0]

0x011A Bits[11:0] = Headphone 1/AUXOUT 4 left balance control register[27:16]

000010000000

Bits[15:0]

Woofer left balance

control register[27:0]

0x011B Bits[15:0] = Headphone 1/AUXOUT 4 left balance control register[15:0]

0000000000000000

Address 0x011C and Address 0x011D Headphone 1/AUXOUT4 Right Balance Control Registers (Default: 0x0080, 0x0000)

These two registers control the balance for the Right Headphone 1 and AUXOUT 4 output.

The balance control words are 28-bit words in twos complement and a 5.23 format. This means there are five bits to the left of the decimal

point of which the most significant bit is the sign bit.

Table 36.

Bit No.

Bit Name

Description

Default

Bits[15:12]

Reserved

Always write as 0 if writing to this register.

0000

Bits[11:0]

Woofer left balance

control register[27:0]

0x011C Bits[11:0] = Headphone 1/AUXOUT 4 right balance

control register[27:16]

000010000000

Bits[15:0]

Woofer left balance

control register[27:0]

0x011D Bits[15:0] = Headphone 1/AUXOUT 4 right balance

control register[15:0]

0000000000000000

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