PI7VD9004ABH

Adaptive EQ 4-channel 960H Video Decoder

Pericom Semiconductor Corporation  

2 

www.pericom.com     

 

Table of Contents

1

 

PI7VD9004ABH Block Diagram............................................................................................................................................. 6

 

2

 

Pin Configuration(128-LQFP)................................................................................................................................................. 7

 

3

 

Pin-out Information.................................................................................................................................................................. 9

 

4

 

Functional Description ...........................................................................................................................................................11

 

4.1

4.2

4.3

4.4

4.5

4.6

4.7

4.8

4.9

4.10

 

PI7VD9004ABH Cascade Mode ......................................................................................................................................17

 

4.11

 

 

5

 

Configuration, Control, and Status Register Map ..............................................................................................................20

 

6

 

Control Register.......................................................................................................................................................................21

 

6.1

6.1.1

 

VIDEO STATUS REGISTER – OFFSET 00H/10H/20H/30H (Default: 00H).....................................................21

 

6.1.2

 

BRIGHTNESS CONTROL REGISTER – OFFSET 01H/11H/21H/31H(Default=00H) ....................................22

 

6.1.3

 

CONTRASTCONTROL REGISTER – OFFSET 02H/12H/22H/32H(Default=64H) ........................................22

 

6.1.4

 

SHARPNESS CONTROL REGISTER – OFFSET 03H/13H/23H/33H(Default=00H) ......................................22

 

6.1.5

 

CHROMA(U) GAIN REGISTER – OFFSET 04H/14H/24H/34H(Default=80H) ..............................................22

 

6.1.6

 

CHROMA(V) GAIN REGISTER – OFFSET 05H/15H/25H/35H(Default=80H) ..............................................23

 

6.1.7

 

HUECONTROL REGISTER – OFFSET 06H/16H/26H/36H(Default=00H)......................................................23

 

6.1.8

 

RESERVED REGISTER– OFFSET07H/17H/27H/37H .........................................................................................23

 

6.1.9

 

RESERVED REGISTER – OFFSET 08H/18H/28H/38H ........................................................................................23

 

6.1.10

 

RESERVED REGISTER – OFFSET09H/19H/29H/39H .........................................................................................23

 

6.1.11

 

RESERVED REGISTER – OFFSET 0AH/1AH/2AH/3AH.....................................................................................23

 

6.1.12

 

RESERVED REGISTER – OFFSET 0BH/1BH/2BH/3BH ......................................................................................23

 

6.1.13

 

RESERVED REGISTER – OFFSET 0CH/1CH/2CH/3CH .....................................................................................23

 

6.1.14

 

RESERVED REGISTER – OFFSET 0DH/1DH/2DH/3DH....................................................................................23

 

6.1.15

 

STANDARD SELECTION REGISTER – OFFSET 0EH/1EH/2EH/3EH(Default=77H) ..................................23

 

6.1.16

 

RESERVEDREGISTER – OFFSET 0FH/1FH/2FH/3FH ........................................................................................23

 

6.1.17

 

RESERVED REGISTER – OFFSET 40H-50H ..........................................................................................................23

 

6.1.18

 

FBITINV REGISTER – OFFSET 51H(Default=00H) .............................................................................................23

 

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