Data Sheet

AD9613

Rev. C | Page 25 of 36

AD8376

AD9613

1µH

1µH

1nF

1nF

VPOS

VCM

15pF

68nH

2.5kΩ║2pF

301Ω

165Ω

165Ω

5.1pF

3.9pF

180nH

1000pF

1000pF

NOTES

1. ALL INDUCTORS ARE COILCRAFT 0603CS COMPONENTS

WITH THE EXCEPTION OF THE 1µH CHOKE INDUCTORS (0603LS).

2. FILTER VALUES SHOWN FOR A 20MHz BANDWIDTH FILTER

CENTERED AT 140MHz.

180nH

220nH

220nH

Figure 50. Differential Input Configuration Using the AD8376 (Filter Values Shown for a 20 MHz Bandwidth Filter Centered at 140 MHz)

VOLTAGE REFERENCE

A stable and accurate voltage reference is built into the AD9613.

The full-scale input range can be adjusted by varying the reference

voltage via SPI. The input span of the ADC tracks reference

voltage changes linearly.

CLOCK INPUT CONSIDERATIONS

For optimum performance, the AD9613 sample clock inputs,

CLK+ and CLK−, should be clocked with a differential signal. The

signal is typically ac-coupled into the CLK+ and CLK− pins via

a transformer or via capacitors. These pins are biased internally

(see Figure 51) and require no external bias. If the inputs are

floated, the CLK− pin is pulled low to prevent spurious clocking.

AVDD

CLK+

4pF

4pF

CLK–

0.9V

Figure 51. Simplified Equivalent Clock Input Circuit

Clock Input Options

The AD9613 has a very flexible clock input structure. Clock

input can be a CMOS, LVDS, LVPECL, or sine wave signal.

Regardless of the type of signal being used, clock source jitter

is of the most concern, as described in the Jitter Considerations

section.

Figure 52 and Figure 53 show two preferable methods for clocking

the AD9613 (at clock rates of up to 625 MHz). A low jitter clock

source is converted from a single-ended signal to a differential

signal using an RF balun or RF transformer.

The RF balun configuration is recommended for clock frequencies

between 125 MHz and 625 MHz, and the RF transformer is

recommended for clock frequencies from 10 MHz to 200 MHz.

The back-to-back Schottky diodes across the transformer secondary

limit clock excursions into the AD9613 to approximately 0.8 V p-p

differential. This limit helps prevent the large voltage swings of

the clock from feeding through to other portions of the AD9613,

while preserving the fast rise and fall times of the signal, which are

critical to low jitter performance.

390pF

390pF

390pF

SCHOTTKY

DIODES: HSMS2822

CLOCK

INPUT

50Ω

100Ω

CLK–

CLK+

ADC

ADT1-1WT, 1:1Z

XFMR

Figure 52. Transformer Coupled Differential Clock (Up to 200 MHz)

390pF

25Ω

25Ω

390pF

390pF

CLOCK

INPUT

CLK–

CLK+

SCHOTTKY

DIODES:

HSMS2822

ADC

Figure 53. Balun-Coupled Differential Clock (Up to 625 MHz)

If a low jitter clock source is not available, another option is to

ac-couple a differential PECL signal to the sample clock input

pins, as shown in Figure 54. The AD9510, AD9511, AD9512,

AD9513, AD9514, AD9515, AD9516, AD9517, AD9518, AD9520,

AD9522, AD9523, AD9524, and ADCLK905/ADCLK907/

ADCLK925 clock drivers offer excellent jitter performance.

100Ω

0.1µF

0.1µF

0.1µF

0.1µF

240Ω

240Ω

PECL DRIVER

50kΩ

50kΩ

CLK–

CLK+

CLOCK

INPUT

CLOCK

INPUT

AD95xx

ADC

Figure 54. Differential PECL Sample Clock (Up to 625 MHz)