40 Device Specifications

TLF11919 – 30

Note

In the system write cycle EN R

WB and CSB are measured at 13V threshold voltage DATA is a TTL compatible input

FIGURE 4-2 System Write Timing Specification

TLF11919 – 31

FIGURE 4-3 LCLK

EN Timing Specification

TLF11919 – 32

FIGURE 4-4 CMOS PCLK Output Skew Timing Specification

TLF11919 – 33

FIGURE 4-5 DIFF PCLK Output Skew Timing Specification

17