поискавой системы для электроныых деталей
  Russian  ▼
ALLDATASHEETRU.COM

X  

Preview PDF HTML

ADN2913 датащи(PDF) 30 Page - Analog Devices

номер детали ADN2913
подробное описание детали  Continuous Rate 6.5 Mbps to 8.5 Gbps Clock and Data Recovery IC with Integrated Limiting Amp/EQ
PDF  37 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

ADN2913 датащи(HTML) 30 Page - Analog Devices

Back Button ADN2913 Datasheet HTML 26Page - Analog Devices ADN2913 Datasheet HTML 27Page - Analog Devices ADN2913 Datasheet HTML 28Page - Analog Devices ADN2913 Datasheet HTML 29Page - Analog Devices ADN2913 Datasheet HTML 30Page - Analog Devices ADN2913 Datasheet HTML 31Page - Analog Devices ADN2913 Datasheet HTML 32Page - Analog Devices ADN2913 Datasheet HTML 33Page - Analog Devices ADN2913 Datasheet HTML 34Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 30 / 37 page
background image
ADN2913
Data Sheet
Rev. A | Page 30 of 37
Disable Output Buffers
The ADN2913 provides the option of disabling the output buffers
for power savings. The clock output buffer can be disabled by
setting Bit CLKOUT_DISABLE (Bit D3 in Register 0x1E) = 1.
This setting reduces the total output power by 30 mW. For a total
of 60 mW of power savings, such as in a low power standby mode,
both the CLKOUT and DATOUT buffers can be disabled together
by setting DATOUT_DISABLE (Bit D4 in Register 0x1E) = 1.
INPUT CONFIGURATIONS
The ADN2913 input stage can work with the signal source in an
ac-coupled or dc-coupled configuration. The ADN2913 supports
one of the following input modes: limiting amplifier, equalizer,
or 0 dB EQ. The ADN2913 can be configured to use any required
input configuration through the I2C bus. Figure 31 shows a block
diagram of the input stage circuit.
The input signal path is configurable with the INPUT_SEL[1:0]
bits (Bits[D6:D5] in Register 0x16). Table 27 shows the
INPUT_SEL[1:0] bits and the input signal configuration.
LOS
DETECT
LA
BYPASS
VCC
FLOAT
VREF
INPUT_SEL[1:0]
RX_TERM_FLOAT
EQ
LOS
PIN
NIN
2
50Ω
50Ω
2.9kΩ
2.9kΩ
Figure 31. Input Stage Block Diagram
Table 27. Input Signal Configuration
Selected Input
INPUT_SEL[1:0]
RX_TERM_FLOAT = 0
RX_TERM_FLOAT = 1
Limiting Amplifier
00
VREF
Not defined
Equalizer
01
VREF
Not defined
0 dB EQ (0 dB Buffer)
10
VCC
Float
Not Defined
11
Not defined
Not defined



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37


датащи скачать

Go To PDF Page


ссылки URL



Вашему бизинису помогли Аллдатащит?  [ DONATE ] 

Что такое Аллдатащит   |   реклама   |   контакт   |   Конфиденциальность   |   Ссылка на техническое описание    |   обмен ссыками   |   поиск по производителю
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com