ADC16061CCVT datasheet(17/20 Pages) NSC

17 / 20 page

Applications Information (Continued)

5.0 LAYOUT AND GROUNDING

Proper grounding and proper routing of all signals are essen-

tial to ensure accurate conversion. Separate analog and

digital ground planes that are connected beneath the

ADC16061 are required to achieve specified performance.

The analog and digital grounds may be in the same layer, but

should be separated from each other and should never over-

lap each other. Separation should be at least 1⁄8 inch, where

possible.

The ground return for the digital supply (DGND I/O ) carries

the ground current for the output drivers. This output current

can exhibit high transients that could add noise to the con-

version process. To prevent this from happening, the DGND

I/O pin should NOT be connected in close proximity to any of

the ADC16061’s other ground pins.

Capacitive coupling between the typically noisy digital

ground plane and the sensitive analog circuitry can lead to

poor performance that may seem impossible to isolate and

remedy. The solution is to keep the analog circuitry sepa-

rated from the digital circuitry and from the digital ground

plane.

Digital circuits create substantial supply and ground current

transients. The logic noise thus generated could have signifi-

cant impact upon system noise performance. The best logic

family to use in systems with A/D converters is one which

employs non-saturating transistor designs, or has low noise

characteristics, such as the 74LS, 74HC(T) and 74AC(T)Q

families. The worst noise generators are logic families that

draw the largest supply current transients during clock or sig-

nal edges, like the 74F and the 74AC(T) families.

Since digital switching transients are composed largely of

high frequency components, total ground plane copper

weight will have little effect upon the logic-generated noise.

This is because of the skin effect. Total surface area is more

important than is total ground plane volume.

An effective way to control ground noise is by connecting the

analog and digital ground planes together beneath the ADC

with a copper trace that is very narrow compared with the

rest of the ground plane. A typical width is 3/16 inch (4 to 5

mm).This narrowing beneath the converter provides a fairly

high impedance to the high frequency components of the

digital switching currents, directing them away from the ana-

log pins. The relatively lower frequency analog ground cur-

rents see a relatively low impedance across this narrow

ground connection.

Generally, analog and digital lines should cross each other at

90 degrees to avoid getting digital noise into the analog path.

To maximize accuracy in high speed, high resolution sys-

tems, however, avoid crossing analog and digital lines alto-

gether. It is important to keep any clock lines isolated from

ALL other lines, including other digital lines. Even the gener-

ally accepted 90 degree crossing should be avoided as even

a little coupling can cause problems at high frequencies.

This is because other lines can introduce phase noise (jitter)

into the clock line, which can lead to degradation of SNR.

Best performance at high frequencies and at high resolution

is obtained with a straight signal path. That is, the signal path

through all components should form a straight line wherever

possible.

Be especially careful with the layout of inductors. Mutual in-

ductance can change the characteristics of the circuit in

which they are used. Inductors should not be placed side by

side, not even with just a small part of their bodies beside

each other.

The analog input should be isolated from noisy signal traces

to avoid coupling of spurious signals into the input. Any ex-

ternal component (e.g., a filter capacitor) connected be-

tween the converter’s input and ground should be connected

to a very clean point in the analog ground plane.

Figure 9 gives an example of a suitable layout. All analog cir-

cuitry (input amplifiers, filters, reference components, etc.)

should be placed on or over the analog ground plane. All

digital circuitry and I/O lines should be placed over the digital

ground plane.

All ground connections should have a low inductance path to

ground.

ADC16061CCVT датащи(PDF) 17 Page - National Semiconductor (TI)

ADC16061CCVT датащи(HTML) 17 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

датащи скачать

ссылки URL