MB9B560R datasheet(97/181 Pages) SPANSION

97 / 181 page

D a t a S h e e t

MB9B560R_DS709-00001-2v0-E, February 2, 2015

CONFIDENTIAL

14.4.4

Operating Conditions of Main PLL (In the Case of Using Main Clock

for Input Clock of PLL)

(VCC = 2.7V to 5.5V, VSS = 0V)

Parameter

Symbol

Value

Unit

Remarks

Min

Typ

Max

PLL oscillation stabilization wait time*

(LOCK UP time)

tLOCK

200

μs

PLL input clock frequency

fPLLI

MHz

PLL multiplication rate

multiplier

PLL macro oscillation clock frequency

fPLLO

200

320

MHz

Main PLL clock frequency*

fCLKPLL

160

MHz

*1: Time from when the PLL starts operating until the oscillation stabilizes.

*2: For more information about Main PLL clock (CLKPLL), see CHPATER 2-1: Clock in FM4

Family Peripheral Manual Main part (MN709-00001).

14.4.5

Operating Conditions of USB PLL (In the Case of Using Main Clock

for Input Clock of PLL)

(VCC = 2.7V to 5.5V, VSS = 0V)

Parameter

Symbol

Value

Unit

Remarks

Min

Typ

Max

PLL oscillation stabilization wait time*

(LOCK UP time)

tLOCK

100

μs

PLL input clock frequency

fPLLI

MHz

PLL multiplication rate

multiplier

PLL macro oscillation clock frequency

fPLLO

200

320

MHz

USB clock frequency*

fCLKSPLL

MHz

After the M frequency division

*1 : Time from when the PLL starts operating until the oscillation stabilizes.

*2 : For more information about USB clock, see CHAPTER 2-2: USB Clock Generation in FM4

Family Peripheral Manual Communication Macro part (MN709-00004).

14.4.6

Operating Conditions of Main PLL (In the Case of Using Built-in

High-speed CR Clock for Input Clock of Main PLL)

(VCC = 2.7V to 5.5V, VSS = 0V)

Parameter

Symbol

Value

Unit

Remarks

Min

Typ

Max

PLL oscillation stabilization wait time*

(LOCK UP time)

tLOCK

200

μs

PLL input clock frequency

fPLLI

3.8

4.2

MHz

PLL multiplication rate

multiplier

PLL macro oscillation clock frequency

fPLLO

190

320

MHz

Main PLL clock frequency*

fCLKPLL

160

MHz

*1: Time from when the PLL starts operating until the oscillation stabilizes.

*2: For more information about Main PLL clock (CLKPLL), see CHAPTER 2-1: Clock in FM4

Family Peripheral Manual Main part (MN709-00001).

Note:

−

Make sure to input to the main PLL source clock, the high-speed CR clock (CLKHC) that the

frequency and temperature has been trimmed.

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