MB9B310R datasheet(5/129 Pages) SPANSION

5 / 129 page

D a t a S h e e t

MB9B310R-DS706-00027-3v0-E, March 11, 2015

CONFIDENTIAL

 Features

 32-bit ARM Cortex-M3 Core

 Processor version: r2p1

 Up to 144MHz Frequency Operation

 Memory Protection Unit (MPU): improves the reliability of an embedded system

 Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 48

peripheral interrupts and 16 priority levels

 24-bit System timer (Sys Tick): System timer for OS task management

 On-chip Memories

[Flash memory]

These series are based on two independent on-chip Flash memories.

 MainFlash

 Up to 512 Kbyte

 Built-in Flash Accelerator System with 16 Kbyte trace buffer memory

 The read access to Flash memory can be achieved without wait cycle up to operation frequency of

72 MHz. Even at the operation frequency more than 72 MHz, an equivalent access to Flash memory

can be obtained by Flash Accelerator System.

 Security function for code protection

 WorkFlash

 32 Kbyte

 Read cycle

 4wait-cycle: the operation frequency more than 72 MHz

 2wait-cycle: the operation frequency more than 40 MHz, and to 72 MHz

 0wait-cycle: the operation frequency to 40 MHz

 Security function is shared with code protection

[SRAM]

This Series contain a total of up to 64 Kbyte on-chip SRAM. This is composed of two independent SRAM

(SRAM0, SRAM1). SRAM0 is connected to I-code bus and D-code bus of Cortex-M3 core. SRAM1 is

connected to System bus.

 SRAM0: Up to 32 Kbyte

 SRAM1: Up to 32 Kbyte

 External Bus Interface

 Supports SRAM, NOR and NAND Flash device

 Up to 8 chip selects

 8-/16-bit Data width

 Up to 25-bit Address bit

 Maximum area size : Up to 256 Mbytes

 Supports Address/Data multiplex

 Supports external RDY input

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