ADC12L030CIWM datasheet(30/36 Pages) NSC

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Application Hints (Continued)

4.0 ANALOG INPUT VOLTAGE RANGE

The ADC12L030/2/4/8’s fully differential ADC generate a

two’s complement output that is found by using the equa-

tions shown below:

for (12-bit) resolution the Output Code =

for (8-bit) resolution the Output Code =

Round off to the nearest integer value between −4096 to

4095 for 12-bit resolution and between −256 to 255 for 8-bit

resolution if the result of the above equation is not a whole

number.

Examples are shown in the table below:

Digital

VREF

−

VIN

−

Output

Code

+2.5V

+1V

+1.5V

0,1111,1111,1111

+2.500V

+2V

0,1100,1100,1101

+2.500V

+2.499V

+2.500V

1,1111,1111,1111

+2.500V

1,0000,0000,0000

5.0 INPUT CURRENT

At the start of the acquisition window (t

A) a charging current

flows into or out of the analog input pins (A/DIN1 and

A/DIN2) depending on the input voltage polarity. The analog

input pins are CH0–CH7 and COM when A/DIN1 is tied to

MUXOUT1 and A/DIN2 is tied to MUXOUT2. The peak value

of this input current will depend on the actual input voltage

applied, the source impedance and the internal multiplexer

switch on resistance. With MUXOUT1 tied to A/DIN1 and

MUXOUT2 tied to A/DIN2 the internal multiplexer switch on

resistance is typically 1.6 k

Ω. The A/DIN1 and A/DIN2 mux

on resistance is typically 750

Ω.

6.0 INPUT SOURCE RESISTANCE

For low impedance voltage sources (<600

Ω), the input

charging current will decay, before the end of the S/H’s ac-

quisition time of 2 µs (10 CCLK periods with f

C = 5 MHz), to

a value that will not introduce any conversion errors. For high

source impedances, the S/H’s acquisition time can be in-

creased to 18 or 34 CCLK periods. For less ADC resolution

and/or slower CCLK frequencies the S/H’s acquisition time

may be decreased to 6 CCLK periods. To determine the

number of clock periods (N

c) required for the acquisition time

with a specific source impedance for the various resolutions

the following equations can be used:

12 Bit + Sign

NC = [RS + 2.3] x fC x 0.824

8 Bit + Sign

NC = [RS + 2.3] x fC x 0.57

Where f

C is the conversion clock (CCLK) frequency in MHz

and R

S is the external source resistance in kΩ. Asanex-

ample, operating with a resolution of 12 Bits+sign,a5MHz

clock frequency and maximum acquistion time of 34 conver-

sion clock periods the ADC’s analog inputs can handle a

source impedance as high as 6 k

Ω. The acquisition time may

also be extended to compensate for the settling or response

time of external circuitry connected between the MUXOUT

and A/DIN pins.

The acquisition time (t

A) is started by a falling edge of SCLK

and ended by a rising edge of CCLK (see Timing Diagrams).

If SCLK and CCLK are asynchronous one extra CCLK clock

period may be inserted into the programmed acquisition time

for synchronization. Therefore with asnychronous SCLK and

CCLK the acquisition time will change from conversion to

conversion.

7.0 INPUT BYPASS CAPACITANCE

External capacitors (0.01 µF–0.1 µF) can be connected be-

tween the analog input pins, CH0–CH7, and analog ground

to filter any noise caused by inductive pickup associated with

long input leads. These capacitors will not degrade the con-

version accuracy.

8.0 NOISE

The leads to each of the analog multiplexer input pins should

be kept as short as possible. This will minimize input noise

and clock frequency coupling that can cause conversion er-

rors. Input filtering can be used to reduce the effects of the

noise sources.

9.0 POWER SUPPLIES

Noise spikes on the V

+ and V

+ supply lines can cause

conversion errors; the comparator will respond to the noise.

The ADC is especially sensitive to any power supply spikes

that occur during the auto-zero or linearity correction. The

minimum power supply bypassing capacitors recommended

are low inductance tantalum capacitors of 10 µF or greater

paralleled with 0.1 µF monolithic ceramic capacitors. More or

different bypassing may be necessary depending on the

overall system requirements. Separate bypass capacitors

should be used for the V

+ and V

+ supplies and placed as

close as possible to these pins.

10.0 GROUNDING

The ADC12L030/2/4/8’s performance can be maximized

through proper grounding techniques. These include the use

of separate analog and digital ground planes. The digital

ground plane is placed under all components that handle

digital signals, while the analog ground plane is placed under

all components that handle analog signals. The digital and

analog ground planes are connected together at only one

point, either the power supply ground or at the pins of the

ADC. This greatly reduces the occurence of ground loops

and noise.

Shown in

Figure 16 is the ideal ground plane layout for the

ADC12L038 along with ideal placement of the bypass ca-

pacitors. The circuit board layout shown in

Figure 16 uses

three bypass capacitors: 0.01 µF (C1) and 0.1 µF (C2) sur-

face mount capacitors and 10 µF (C3) tantalum capacitor.

11.0 CLOCK SIGNAL LINE ISOLATION

The ADC12L030/2/4/8’s performance is optimized by routing

the analog input/output and reference signal conductors as

far as possible from the conductors that carry the clock sig-

nals to the CCLK and SCLK pins. Ground traces parallel to

the clock signal traces can be used on printed circuit boards

to reduce clock signal interference on the analog input/

output pins.

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