ADC12D040 datasheet(16/22 Pages) NSC

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Functional Description

Operating on a single +5V supply, the ADC12D040 uses a

pipelined architecture and has error correction circuitry to

help ensure maximum performance. The differential analog

input signal is digitized to 12 bits. The reference input is

buffered to ease the task of driving that pin.

The output word rate is the same as the clock frequency,

which can be between 100 kSPS and 55 MSPS (typical).

The analog input voltage is acquired at the rising edge of the

clock and the digital data for a given sample is delayed by

the pipeline for 6 clock cycles.

A logic high on the power down (PD) pin reduces the con-

verter power consumption to 75 mW.

Applications Information

1.0 OPERATING CONDITIONS

We recommend that the following conditions be observed for

operation of the ADC12D040:

4.75V

≤ V

≤ 5.25V

D =VA

2.35V

≤ V

100 kHz

≤ f

CLK

≤ 55 MHz

1.0V

≤ V

REF

≤ 2.2V

1.1 Analog Inputs

The ADC12D040 has two analog signal inputs, V

IN+ and

IN−. These two pins form a differential input pair. There is

one reference input pin, V

REF.

1.2 Reference Pins

The ADC12D040 is designed to operate with a 2.0V refer-

ence, but performs well with reference voltages in the range

of 1.0V to 2.2V. Lower reference voltages will decrease the

signal-to-noise ratio (SNR) of the ADC12D040. Increasing

the reference voltage (and the input signal swing) beyond

2.2V will degrade THD for a full-scale input. It is very impor-

tant that all grounds associated with the reference voltage

and the input signal make connection to the analog ground

plane at a single point to minimize the effects of noise

currents in the ground path.

The three Reference Bypass Pins (V

RP,VRM and VRN) are

made available for bypass purposes only. These pins should

each be bypassed to ground with a 0.1 µF capacitor. DO

NOT LOAD these pins.

1.3 Signal Inputs

The signal inputs are V

IN+ and VIN−. The input signal, VIN,is

defined as

IN =(VIN+)– (VIN−)

Figure 2 shows the expected input signal range.

Note that the common mode input voltage range is 1V to 3V

with a nominal value of V

A/2. The input signals should re-

main between ground and 4V.

The Peaks of the individual input signals (V

IN+ and VIN−)

should each never exceed the voltage described as

IN+,VIN− =VREF/2+VCM

≤ 4V (differential)

to maintain THD and SINAD performance.

The ADC12D040 performs best with a differential input with

each input centered around V

CM. The peak-to-peak voltage

swing at both V

IN+ and VIN− should not exceed the value of

the reference voltage or the output data will be clipped. The

two input signals should be exactly 180˚ out of phase from

each other and of the same amplitude. For single frequency

inputs, angular errors result in a reduction of the effective full

scale input. For a complex waveform, however, angular

errors will result in distortion.

For angular deviations of up to 10 degrees from these two

signals being 180 out of phase, the full scale error in LSB

can be described as approximately

FS = dev

1.79

Where dev is the angular difference between the two signals

having a 180˚ relative phase relationship to each other (see

Figure 3). Drive the analog inputs with a source impedance

less than 100

Ω.

For differential operation, each analog input signal should

have a peak-to-peak voltage equal to the input reference

voltage, V

REF, and be centered around VCM. For single

ended operation, one of the analog inputs should be con-

nected to the d.c. common mode voltage of the driven input.

The peak-to-peak differential input signal should be twice the

reference voltage to maximize SNR and SINAD performance

(Figure 2b). For example, set V

REF to 1.0V, bias VIN− to 1.0V

and drive V

IN+ with a signal range of 0V to 2.0V. Because

very large input signal swings can degrade distortion perfor-

mance, better performance with a single-ended input can be

obtained by reducing the reference voltage when maintain-

ing a full-range output. Tables 1, 2 indicate the input to

output relationship of the ADC12D040.

20046011

FIGURE 2. Expected Input Signal Range

20046012

FIGURE 3. Angular Errors Between the Two Input

Signals Will Reduce the Output Level

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