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ADC12130CIWM датащи(PDF) 8 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
номер детали ADC12130CIWM
подробное описание детали  Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold
PDF  41 Pages
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производитель  NSC [National Semiconductor (TI)]
домашняя страница  http://www.national.com
Logo NSC - National Semiconductor (TI)

ADC12130CIWM датащи(HTML) 8 Page - National Semiconductor (TI)

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DC and Logic Electrical Characteristics (Continued)
The following specifications apply for (V
+ =V
A+=VD+ = +5V, VREF+ = +4.096V, and fully-differential input with fixed 2.048V
common-mode voltage) or (V
+ =V
A+=VD+ = +3.3V, VREF+ = +2.5V and fully-differential input with fixed 1.250V
common-mode voltage), V
REF− = 0V, 12-bit + sign conversion mode, source impedance for analog inputs, VREF− and VREF+
≤ 25Ω,f
CK =fSK = 5 MHz, and 10 (tCK) acquisition time unless otherwise specified. Boldface limits apply for TA =TJ =
T
MIN to TMAX; all other limits TA =TJ = 25˚C. (Notes 7, 8, 9)
Symbol
Parameter
Conditions
Typical
(Note
10)
V
+ =V
A+=
V
+ =V
A+ =
Units
(Limits)
V
D+ = 3.3V
V
D+=5V
Limits
Limits
(Note 11)
(Note 11)
DO, EOC AND DOR DIGITAL OUTPUT CHARACTERISTICS
−I
SC
Output Short
Circuit Sink
Current
V
OUT =VD+16
mA
POWER SUPPLY CHARACTERISTICS
I
D+
Digital Supply
1.5
2.5
mA (max)
Current
CS = HIGH, Powered Down, CCLK on
600
µA
CS = HIGH, Powered Down, CCLK off
20
µA
I
A+
Positive Analog
3.0
4.0
mA (max)
Supply Current
CS = HIGH, Powered Down, CCLK on
10
µA
CS = HIGH, Powered Down, CCLK off
0.1
µA
I
REF
Reference Input
Current
CS = HIGH, Powered Down, CCLK on
70
µA
CS = HIGH, Powered Down, CCLK off
0.1
µA
AC Electrical Characteristics
The following specifications apply for (V
+ =V
A+=VD+ = +5V, VREF+ = +4.096V, and fully-differential input with fixed 2.048V
common-mode voltage) or (V
+ =V
A+=VD+ = +3.3V, VREF+ = +2.5V and fully-differential input with fixed 1.250V
common-mode voltage), V
REF− = 0V, 12-bit + sign conversion mode, source impedance for analog inputs, VREF− and VREF+
≤ 25Ω,f
CK =fSK = 5 MHz, and 10 (tCK) acquisition time unless otherwise specified. Boldface limits apply for TA =TJ =
T
MIN to TMAX; all other limits TA =TJ = 25˚C. (Note 17)
Symbol
Parameter
Conditions
Typical
Limits
Units
(Note
10)
(Note
11)
(Limits)
f
CK
Conversion Clock
10
5
MHz (max)
(CCLK) Frequency
1
MHz (min)
f
SK
Serial Data Clock
10
5
MHz (max)
SCLK Frequency
0
Hz (min)
Conversion Clock
40
% (min)
Duty Cycle
60
% (max)
Serial Data Clock
40
% (min)
Duty Cycle
60
% (max)
t
C
Conversion Time
12-Bit + Sign or 12-Bit
44(t
CK)
44(t
CK)
(max)
8.8
µs (max)
www.national.com
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