ADC12062 datasheet(14/20 Pages) NSC

14 / 20 page

Applications Information (Continued)

30 ANALOG MULTIPLEXER

The ADC12062 has an input multiplexer that is controlled by

the logic level on pin S0 when EOC goes low as shown in

Figures 1 and 2 Multiplexer setup and hold times with re-

spect to the SH input can be determined by these two

equations

tMS (wrt SH) e tMS b tEOC (min) e 50 b 60 eb10 ns

tMH (wrt SH) e tMH a tEOC (max) e 50 a 125 e 175 ns

Note that tMS (wrt SH) is a negative number this indicates

that the data on S0 must become valid within 10 ns after

SH goes low in order to meet the setup time requirements

S0 must be valid for a length of

(tMH a tEOC (max)) b (tMS b tEOC (min)) e 185 ns

Table I shows how the input channels are assigned

TABLE I ADC12062 Input

Multiplexer Programming

Channel

0VIN1

1VIN2

The output of the multiplexer is available to the user via the

MUX OUT pin This output allows the user to perform addi-

tional signal processing such as filtering or gain before the

signal is returned to the ADC IN input and digitized If no

additional signal processing is required the MUX OUT pin

should be tied directly to the ADC IN pin

See Section 90 (APPLICATIONS) for a simple circuit that

will alternate between the two inputs while converting at full

speed

40 REFERENCE INPUTS

In addition to the fully differential VREFa and VREFb refer-

ence inputs used on most National Semiconductor ADCs

the ADC12062 has two sense outputs for precision control

of the ladder voltage These sense inputs compensate for

errors due to IR drops between the reference source and

the ladder itself The resistance of the reference ladder is

typically 750X The parasitic resistance (RP) of the package

leads bond wires PCB traces etc can easily be 05X to

10X or more This may not be significant at 8-bit or 10-bit

resolutions but at 12 bits it can introduce voltage drops

causing offset and gain errors as large as 6 LSBs

The ADC12062 provides a means to eliminate this error by

bringing out two additional pins that sense the exact voltage

at the top and bottom of the ladder With the addition of two

op amps the voltages on these internal nodes can be

forced to the exact value desired as shown in

Figure 10

TLH11490 – 20

FIGURE 10 Reference Ladder Force and Sense Inputs

ADC12062 датащи(PDF) 14 Page - National Semiconductor (TI)

ADC12062 датащи(HTML) 14 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

датащи скачать

ссылки URL