Timing Diagram

Functional Description

The ADC10321 maintains excellent dynamic performance

for input signals up to half the clock frequency. The use of an

internal sample-and-hold amplifier (SHA) enables sustained

dynamic performance for signals of input frequency beyond

the clock rate, lowers the converter’s input capacitance and

reduces the number of external components required.

The analog signal at V

by V

MSPS. Input voltages below V

word to consist of all zeroes. Input voltages above V

will cause the output word to consist of all ones. V

a range of 2.3 to 4.0 Volts, while V

to 3.0 Volts. V

positive than V

Data is acquired at the falling edge of the clock and the digi-

tal equivalent of that data is available at the digital outputs

2.0 clock cycles plus t

long as the clock signal is present at pin 9 and the PD pin is

low. The Output Enable pin (OE), when low, enables the out-

put pins. The digital outputs are in the high impedance state

when the OE pin is low or the PD pin is high.

DS100897-15

FIGURE 1. ADC10321 Timing Diagram

DS100897-17

FIGURE 2. AC Test Circuit

DS100897-16

FIGURE 3. t

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