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2015-12-0001

PT0280-8

12/11/15

28

PT7C43390/43390C

Real-time Clock Module

acknowledgment signal back. For example, as seen in below Figure, in case that the PT7C43390 is the device working for

receiving data and the master device is the one working for sending data; when the 8th clock pulse falls, the master device releases

the SDA line. After that, the PT7C43390 sends an acknowledgment signal back, and set the SDA line to "L" at the 9th clock pulse.

The PT7C43390 does not output an acknowledgment signal is that the access is not being done regularly.

Output Timing of Acknowledgment Signal

 Data reading in the PT7C43390

After detecting a start condition, the PT7C43390 receives device code and command. The PT7C43390 enters the read-data mode

by the read / write bit "1". The data is output from B7 in 1-byte. Input an acknowledgment signal from the master device every

moment that the PT7C43390 outputs 1-byte data. However, do not input an acknowledgment signal (input NO_ACK) for the last

data-byte output from the master device. This procedure notifies the completion of reading. Next, input a stop condition to the

PT7C43390 to finish access.

Example of Data Reading 1 (1-Byte Data Register)