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PI6LC48P03

Rev. C

5/7/2015

PI6LC48P03

3-Output LVPECL Networking Clock Generator

Pinout Table

Pin No.

Pin Name

I/O Type

Description

1

NB_SEL0

Input

Pull-down Bank B Output Divider Select

2

PLL_ByPass#

Input

Pull-up

Active Low PLL Bypass

3

M_reset

Input

Pull-down Master Reset. When HIGH, CLKx goes to “low” and CLKx# goes to

“high”; When LOW outputs are enabled.

4

VDDOA

Power

Bank A Output Power Supply

5, 6

CLKA, CLKA#

Output

Bank A LVPECL Output Clock

7

OEB

Input

Pull-up

Bank B Output Enable. When LOW, output is differential low.

8

OEA

Input

Pull-up

Bank A Output Enable. When LOW, output is differential low.

9

FBN

Input

Pull-down Feedback Divider Select

10

VDDA

Power

Analog Power Supply

11

VDD

Power

Core Power Supply

12

NA_SEL0

Input

Pull-up

Bank A Output Divider Select

13

NA_SEL1

Input

Pull-down Bank A Output Divider Select

14

GND

Ground

Ground

15, 16

XTAL_OUT,

XTAL_IN

Crystal

Crystal Input and Output

17

Ref_IN

Input

Pull-down CMOS Reference Clock Input

18

IN_SEL#

Input

Pull-up

When HIGH, Crystal is selected; When LOW, reference input is

selected.

19, 20

CLKB1#, CLKB1 Output

Bank B LVPECL Output Clock 1

21, 22

CLKB0#, CLKB0 Output

Bank B LVPECL Output Clock 0

23

VDDOB

Power

Bank B Output Power Supply

24

NB_SEL1

Input

Pull-up

Bank B Output Divider Select

Pin Configuration

1

2

3

VDDOA

4

CLKA

5

M_reset

6

OEB

7

Ref_IN

8

CLKA#

NB_SEL1

CLKB0

CLKB0#

CLKB1#

IN_SEL#

OEA

24

23

22

21

20

19

18

17

NB_SEL0

PLL_ByPass#

CLKB1

VDDOB

XTAL_IN

9

FBN

16

XTAL_OUT

10

VDDA

15

GND

11

VDD

14

NA_SEL1

12

13

NA_SEL0

15-0059