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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ADC08161CIWM датащи(PDF) 4 Page - National Semiconductor (TI) |
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ADC08161CIWM датащи(HTML) 4 Page - National Semiconductor (TI) |
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4 / 15 page  AC Electrical Characteristics The following specifications apply for V + = 5V, t r = tf = 10 ns, VREF+ = 5V, VREF− = 0V unless otherwise specified. Boldface limits apply for T A = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C. Symbol Parameter Conditions Typical (Note 7) Limit (Note 8) Units (Limit) t WR Write Time Mode Pin to V + 100 100 ns (min) ( Figures 2, 3, 4) t RD Read Time (Time from Rising Edge Mode Pin to V +,(Figure 2) 350 350 ns (min) of WR to Falling Edge of RD ) t RDW RD Width Mode Pin to GND ( Figure 5 ) 200 250 ns (min) 400 400 ns (max) t CONV WR -RD Mode Conversion Time Mode Pin to V +,(Figure 2 ) 500 560 ns (max) (t WR +tRD +tACC1) t CRD RD Mode Conversion Time Mode Pin to GND, ( Figure 1 ) 655 900 ns (max) t ACCO Access Time (Delay from Falling C L ≤ 100 pF, Mode Pin to GND 640 900 ns (max) Edge of RD to Output Valid) ( Figure 1 ) t ACC1 Access Time (Delay from C L ≤ 10 pF 45 ns Falling Edge of RD C L = 100 pF 50 110 ns (max) to Output Valid) Mode Pin to V +,t RD ≤ tINTL ( Figure 2 ) t ACC2 Access Time (Delay from C L ≤ 10 pF 25 ns Falling Edge of RD C L = 100 pF 30 55 ns (max) to Output Valid) t RD > tINTL, ( Figures 3, 5) t 1H,t0H TRI-STATE® Control R L = 3kΩ,CL = 10 pF (Delay from Rising Edge ( Figures 1, 2, 3, 4, 5)30 60 ns (max) of RD to HI-Z State) t INTL Delay from Rising Edge of Mode Pin = V +,C L = 50 pF 520 690 ns (max) WR to Falling Edge of INT ( Figures 3, 4) t INTH Delay from Rising Edge of C L = 50 pF, 50 95 ns (max) RD to Rising Edge of INT ( Figures 1, 2, 3, 5) t INTH Delay from Rising Edge of C L = 50 pF, (Figure 4)45 95 ns (max) WR to Rising Edge of INT t RDY Delay from CS to RDY Mode Pin = 0V, C L = 50 pF, 25 45 ns (max) R L = 3kΩ,(Figure 1) t ID Delay from INT R L = 3kΩ,CL = 100 pF 0 15 ns (max) to Output Valid ( Figure 4) t RI Delay from RD to INT Mode Pin = V +,t RD ≤ tINTL 60 115 ns (max) ( Figure 2) t N Time between End of RD ( Figures 1, 2, 3, 4, 5)50 50 ns (min) and Start of New Conversion t CSS CS Setup Time ( Figures 1, 2, 3, 4, 5)0 0 ns (max) t CSH CS Hold Time ( Figures 1, 2, 3, 4, 5)0 0 ns (max) DC Electrical Characteristics The following specifications apply for V + = 5V unless otherwise specified. Boldface limits apply for T A = TJ = TMIN to TMAX; all other limits T A = TJ = 25˚C. Symbol Parameter Conditions Typical (Note 7) Limit (Note 8) Units (Limit) V IH Logic “1” Input Voltage V + = 5.5 V CS, WR, RD, A0, A1, A2 Pins 2.0 V (min) Mode Pin 3.5 www.national.com 4 |
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