Summary TC90104AFG

Page 3

Rev.1.00

2015/10/16

4. Pin Descriptions

Pin No.

Pin Name

Pin Function

Pin type

Standard withstand

voltage [V]

Processing at

unused time

1

VDDDA

2.5 V power supply for DAC

VDD

2.5

-

2

PLLIN

Input of PLL circuit for clock

IN

2.5

-

3

VDDPLL

2.5 V power supply for PLL circuit

VDD

2.5

-

4

VCOFIL

VCO control bias for PLL circuit

Bias

2.5

-

5

VSSPLL

GND for PLL circuit

VSS

0

-

6

VDDXO

2.5V Power supply for X’tal circuit

VDD

2.5

-

7

XOIN

Input for X’tal circuit

IN

2.5

-

8

XOOUT

Output for X’tal circuit

OUT

2.5

-

9

VSSXO

GND for X’tal circuit

GND

0

-

10

VDD-D3

1.5 V power supply for Logic circuit

VDD

1.5

-

11

SDA

I / O

5

-

12

SCL

IN

5

-

13

RESET

System reset

IN

3.3

-

14

VSS

Digital GND

GND

0

-

15

TESTout1

TEST output terminal 1

OUT

3.3

Open

16

VD

VD output

OUT

3.3

Open

17

HD

HD output

OUT

3.3

Open

18

CLK

Clock signal output

OUT

3.3

-

19

VDD-IO3

3.3 V power supply for I/O circuit

VDD

3.3

-

20

Y7

Y7 signal output (MSB)

*1

OUT

3.3

-

21

Y6

Y6 signal output

*1

OUT

3.3

-

22

VSS

Digital GND

GND

0

-

23

VDD-D2

1.5V power supply for logic circuit

VDD

1.5

-

24

Y5

Y5 signal output

*1

OUT

3.3

-

25

Y4

Y4 signal output

*1

OUT

3.3

-

26

VDD-IO2

3.3V power supply for I/O circuit

VDD

3.3

-

27

Y3

Y3 signal output

*1

OUT

3.3

-

28

Y2

Y2 signal output

*1

OUT

3.3

-

29

VSS

Digital GND

GND

0

-

30

Y1

Y1 signal output

OUT

3.3

-

31

Y0

Y0 signal output

OUT

3.3

-

32

TESTout2

TEST output terminal 2

OUT

3.3

Open

*1: It is available for SAV/EAV implantation when input signal is CVBS or YCbCr(D1) and output is ITU-R BT.656 format.

It needs to use HD/VD output mode because it is not available for SAV/EAV implantation when output is D2 signal

(54MHz 8bit).