7

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P-0.1

07/02/12

PI6C49006

Embedded Clock Generator

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Byte 1: Control Register

Bit

Description

Type

Power Up Condi-

tion

Output(s) Affected

Notes

7

OE for 25M_Out Diff

RW

1

25M_Out Diff

0 = disabled

1 = enabled

6

OE for 25M_Out2

RW

1

25M_Out2

0 = disabled

1 = enabled

5

OE for 25M_Out1

RW

1

25M_Out1

0 = disabled

1 = enabled

4

OE for 125_Out0

RW

1

125_Out0

0 = disabled

1 = enabled

3

OE for OutB_1

RW

1

OutB_1

0 = disabled

1 = enabled

2

OE for OutB_0

RW

1

OutB_0

0 = disabled

1 = enabled

1

Spread Spectrum Selection for

100MHz HCSL PCI Express clocks

Bit 1: SS1, Bit 0:SS0

RW

0

All 100MHz HCSL PCI

Express outputs

See Selection Table

2 - Spread Spec-

trum

0

RW

0

Byte 2: Control Register

Bit

Description

Type

Power Up Condi-

tion

Output(s) Affected

Notes

7 to 0

Reserved

R

Undefined

Not Applicable

Byte 0 - Bit 6 and Bit 5 Functionality

Bit 6

Bit 5

Description

0

X

(RESET# = "H" will enable all outputs; SMBus cannot control each output.)

1

0

Disables all outputs and tri-states the outputs, RESET# HW pin/signal = DO NOT CARE

1

1

Enable outputs according to the SMBus default values; SMBus can control each output.

RESET# HW pin/signal, FS1, FS2, FS3 and FS4 = DON'T CARE

12-0212