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DM9602N датащи(PDF) 4 Page - National Semiconductor (TI) |
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DM9602N датащи(HTML) 4 Page - National Semiconductor (TI) |
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4 / 8 page ![]() Operating Rules (Continued) B Use with high inverse leakage current electrolytic ca- pacitors The diode in this configuration prevents high inverse leakage currents through the capacitor by preventing an inverse voltage across the capacitor The use of this configuration is not recommended with retriggera- ble operation t 03 RCX TLF6611 – 5 C Use to obtain extended pulse widths This configuration can be used to obtain extended pulse widths because of the larger timing resistor al- lowed by beta multiplication Electrolytics with high in- verse leakage currents can be used R k RX (07) (hFE Q1) or k 25 MX whichever is the lesser RX (min) k RY k RX (max) (5 kX s RY s 10 kX is recommended) Q1 NPN silicon transistor with hFE requirements of above equations such as 2N5961 or 2N5962 t 03 RCX TLF6611 – 6 This configuration is not recommended with retriggera- ble operation 5 To obtain variable pulse width by remote trimming the following circuit is recommended TLF6611 – 7 6 Under any operating condition CX and RX (min) must be kept as close to the circuit as possible to minimize stray capacitance and reduce noise pickup 7 Input Trigger Pulse Rules (See Triggering Truth Table) TLF6611 – 8 Input to Pin 5(11) (Pin 3(13) e HIGH) Pin 4(12) e LOW t1 t3 e Min Positive Input Pulse Width l 40 ns t2 t4 e Min Negative Input Pulse Width l 40 ns TLF6611 – 9 Input to Pin 4(12) (Pin 3(13) e HIGH) Pin 5(11) e HIGH 8 The retriggerable pulse width is calculated as shown be- low tW e t a tPLH e KRX CX 1a 1R X J atPLH TLF6611 – 10 The retrigger pulse width is equal to the pulse width (t) plus a delay time For pulse widths greater than 500 ns tW can be approximated as t Retriggering will not occur if the retrigger pulse comes within 03 CX (ns) after the initial trigger pulse (ie during the discharge cycle) 9 Reset OperationAn overriding clear (active LOW level) is provided on each one shot By applying a LOW to the reset any timing cycle can be terminated or any new cy- cle inhibited until the LOW reset input is removed Trigger inputs will not produce spikes in the output when the re- set is held LOW TLF6611 – 11 10 VCC and Ground wiring should conform to good high frequency standards so that switching transients on VCC and Ground leads do not cause interaction between one shots Use of a 001 to 01 mF bypass capacitor be- tween VCC and Ground located near the DM9602 is rec- ommended For further detailed device characteristics and output performance please refer to the NSC one-shot application note AN-366 4 |
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