Time

TPS22981

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SLVSBM6B – DECEMBER 2012 – REVISED NOVEMBER 2015

Feature Description (continued)

Figure 5. Output Voltage Transitions (Timing Transitions are 10% to > 90%)

7.3.5 Digital Control Signals

The voltage at OUT is controlled by two input digital logic signals, EN and HV_EN. HV_EN controls the state of

the VHV switch and EN controls the state of V3P3 switch. Table 1 lists the possible output states given the

conditions of the digital logic signals and the device is not in UVLO. See Table 2 for a more complete description

including both UVLO conditions.

Table 1. Output State of OUT Given the States EN and HV_EN

EN

HV_EN

OUT

0

0

OPEN

0

1

OPEN

1

0

V3P3

1

1

VHV

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