Functional Description

The two 8-bit shift registers have a common clock input (pin

9) and separate clock inputs (pins 10 and 7) The clocking

of each register is controlled by the OR function of the sep-

arate and the common clock input Each register is com-

posed of eight clocked RS masterslave flip-flops and a

number of gates The clock OR gate drives the eight clock

inputs of the flip-flops in parallel When the two clock inputs

(the separate and the common) to the OR gate are LOW

the slave latches are steady but data can enter the master

latches via the R and S input During the first LOW-to-HIGH

transition of either or both simultaneously of the two clock

inputs the data inputs (R and S) are inhibited so that a later

change in input data will not affect the master then the now

trapped information in the master is transferred to the slave

When the transfer is complete both the master and the

slave are steady as long as either or both clock inputs re-

main HIGH During the HIGH-to-LOW transition of the last

remaining HIGH clock input the transfer path from master

to slave is inhibited first leaving the slave steady in its pres-

ent state The data inputs (R and S) are enabled so that new

data can enter the master Either of the clock inputs can be

used as clock inhibit inputs by applying a logic HIGH signal

Each 8-bit shift register has a 2-input multiplexer in front of

the serial data input The two data inputs D0 and D1 are

controlled by the data select input (S) following the Boolean

expression

An asynchronous master reset is provided which when acti-

vated by a LOW logic level will clear all 16 stages indepen-

dently of any other input signal

Shift Select Table

Inputs

Output

S

LL

X

L

LH

X

H

HX

L

L

HX

H

H

Logic Diagram

TLF10200 – 3

4