NJW4160 datasheet(21/22 Pages) NJRC

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NJW4160

- 21 -

Ver.2014-04-01

Compensation Design (Continued)

Poles and zeros due to the inductance and output capacitor

Double poles fP(LC) are generated by the inductance and output capacitor. Simultaneously, single zeros fZ(ESR) are

generated by the output capacitor and ESR. Each pole and zero is expressed by the following formula.

ESR

OUT

)

ESR

(

OUT

)

(

If the ESR of the output capacitor is high, fZ(ESR) will be located in the vicinity of fP(LC). In an application such as this,

the zero fZ(ESR) compensates the double poles fP(LC), resulting in a tendency for stability to be readily maintained.

However, if the ESR of the output capacitor is low, fZ(ESR) shifts to the high region, and the phase is shifted -180 by

fP(LC).The NJW4160 compensation circuit enables compensation to be realized by using zeros fZ1 and fZ2.

Poles and zeros due to error amplifier

The single poles and zeros generated by the error amplifier

are obtained using the following formula.

Zero

Pole

(Av: Amplifier Open Loop Gain=80dB)

(Option)

fZ1 and fZ2 are located on both sides of fP(LC).

Because the inductance and output capacitor vary, they are

each set using the following as a rough guide.

fP(LC) 0.5-fold – 0.9-fold

fP(LC) 1.1-fold – 2.0-fold

There is also a method in which fZ1 and fZ2 are located at positions lower than even fP(LC). Because there is a

tendency for the phase shift to increase and the gain to rise, it can be expected that the response will improve.

However, there is a tendency for the phase margin to become insufficient, so care is necessary.

fP1 creates poles in the low frequency region due to the Miller effect of the error amplifier. The stability becomes

better as fP1 becomes lower. On the other hand, the frequency characteristics do not improve, so the response is

adversely affected. fP1 is set using a frequency gain of 20 dB for fP(LC) as a rough guide.

If the open loop gain of the error amplifier is made 80 dB, design is carried out using fP1 < fP(LC) 10

3 (= 60 dB) as a

rough guide.

Above several 100 kHz, various poles are generated, so the upper limit of the frequency range where the loop

gain is 0 dB is set to fifth (1/5) to tenth (1/10) of oscillation frequency. The fZ(ESR) in the high frequency region

sometimes causes a loop gain to be generated (See Fig.13 Loop Gain “). Using fP2 and fP3, perform adjustment with

the NJW4160 mounted in an actual unit, so as to adequately reduce the loop gain in the high frequency region.

Fig. 13. Loop Gain examples

fZ1 or fZ2

fP(LC)

fP2 fP3 fZ(ESR)

Gain (dB)

LC Gain

Loop

Gain

Compensation

Gain

-40dB/dec

-20dB/dec

0dB frequency

Double

pole

fP1

* Gain increase

due to Zero

NJW4160 Application Manual

Technical Information

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