IN

OUT

OUT

OUT(LL)

SW

IN

(V

V

)

V

1

I

2

L

f

V

u

u

u

u

TPS563201, TPS563208

SLVSD90 – DECEMBER 2015

www.ti.com

Feature Description (continued)

7.3.2 Pulse Skip Control (TPS563201)

The TPS563201 is designed with advanced Eco-mode to maintain high light load efficiency. As the output current

decreases from heavy load condition, the inductor current is also reduced and eventually comes to point that its

rippled valley touches zero level, which is the boundary between continuous conduction and discontinuous

conduction modes. The rectifying MOSFET is turned off when the zero inductor current is detected. As the load

current further decreases the converter runs into discontinuous conduction mode. The on-time is kept almost the

same as it was in the continuous conduction mode so that it takes longer time to discharge the output capacitor

with smaller load current to the level of the reference voltage. This makes the switching frequency lower,

proportional to the load current, and keeps the light load efficiency high. The transition point to the light load

(1)

7.3.3 Soft Start and Pre-Biased Soft Start

The TPS563201 and TPS563208 have an internal 1-ms soft-start. When the EN pin becomes high, the internal

soft-start function begins ramping up the reference voltage to the PWM comparator.

If the output capacitor is pre-biased at startup, the devices initiate switching and start ramping up only after the

converters ramp up smoothly into regulation point.

7.3.4 Current Protection

The output over-current limit (OCL) is implemented using a cycle-by-cycle valley detect control circuit. The switch

current is monitored during the OFF state by measuring the low-side FET drain to source voltage. This voltage is

proportional to the switch current. To improve accuracy, the voltage sensing is temperature compensated.

During the on time of the high-side FET switch, the switch current increases at a linear rate determined by Vin,

Vout, the on-time and the output inductor value. During the on time of the low-side FET switch, this current

above the OCL level, the converter maintains low-side FET on and delays the creation of a new set pulse, even

the voltage feedback loop requires one, until the current level becomes OCL level or lower. In subsequent

switching cycles, the on-time is set to a fixed value and the current is monitored in the same manner.

There are some important considerations for this type of over-current protection. The load current is higher than

the over-current threshold by one half of the peak-to-peak inductor ripple current. Also, when the current is being

limited, the output voltage tends to fall as the demanded load current may be higher than the current available

from the converter. This may cause the output voltage to fall. When the VFB voltage falls below the UVP

threshold voltage, the UVP comparator detects it. And then, the device will shut down after the UVP delay time

(typically 24 µs) and re-start after the hiccup time (typically 15 ms).

When the over current condition is removed, the output voltage returns to the regulated value.

7.3.5 Undervoltage Lockout (UVLO) Protection

UVLO protection monitors the internal regulator voltage. When the voltage is lower than UVLO threshold voltage,

the device is shut off. This protection is non-latching.

7.3.6 Thermal Shutdown

The device monitors the temperature of itself. If the temperature exceeds the threshold value (typically 172°C),

the device is shut off. This is a non-latch protection.

10

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