XRT72L13 datasheet(7/370 Pages) EXAR

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XRT72L13

M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC

PRELIMINARY

REV. P1.0.6

M12 DS2 # 1 LOOP-BACK STATUS REGISTER (ADDRESS = 0XA0) .............................................................. 158

DS2 # 1 FRAMER INTERRUPT ENABLE REGISTER (ADDRESS = 0XA1) ......................................................... 158

DS2 # 1 FRAMER INTERRUPT REGISTER (ADDRESS = 0XA2) ..................................................................... 159

DS2 # 1 FRAMER STATUS REGISTER (ADDRESS = 0XA3) ......................................................................... 160

DS2 # 2 FRAMER INTERRUPT ENABLE REGISTER (ADDRESS = 0XA4) ......................................................... 160

DS2 # 2 FRAMER INTERRUPT REGISTER (ADDRESS = 0XA5) ..................................................................... 161

DS2 # 2 FRAMER STATUS REGISTER (ADDRESS = 0XA6) ......................................................................... 162

DS2 # 3 FRAMER INTERRUPT ENABLE REGISTER (ADDRESS = 0XA7) ......................................................... 162

DS2 # 3 FRAMER INTERRUPT REGISTER (ADDRESS = 0XA8) .................................................................... 163

DS2 # 3 FRAMER STATUS REGISTER (ADDRESS = 0XA9) ......................................................................... 164

DS2 # 4 FRAMER INTERRUPT ENABLE REGISTER (ADDRESS = 0XAA) ........................................................ 164

DS2 # 4 FRAMER INTERRUPT ENABLE REGISTER (ADDRESS = 0XAB) ........................................................ 165

DS2 # 4 FRAMER STATUS REGISTER (ADDRESS = 0XAC) ........................................................................ 166

DS2 # 5 FRAMER INTERRUPT ENABLE REGISTER (ADDRESS = 0XAD) ........................................................ 166

DS2 # 5 FRAMER INTERRUPT ENABLE REGISTER (ADDRESS = 0XAF) ........................................................ 167

DS2 # 5 FRAMER STATUS REGISTER (ADDRESS = 0XAF) ......................................................................... 168

DS2 # 6 FRAMER INTERRUPT ENABLE REGISTER (ADDRESS = 0XB0) ........................................................ 168

DS2 # 6 FRAMER INTERRUPT REGISTER (ADDRESS = 0XB2) .................................................................... 169

DS2 # 6 FRAMER STATUS REGISTER (ADDRESS = 0XB2) ......................................................................... 170

DS2 # 7 FRAMER INTERRUPT ENABLE REGISTER (ADDRESS = 0XB3) ........................................................ 170

DS2 # 7 FRAMER INTERRUPT REGISTER (ADDRESS = 0XB5) .................................................................... 171

DS2 # 7 FRAMER STATUS REGISTER (ADDRESS = 0XB5) ......................................................................... 171

3.0 The Microprocessor Interface Block ............................................................................................ 173

Figure 46. Simple Block Diagram of the Microprocessor Interface Block, within the Framer IC 173

3.1 THE MICROPROCESSOR INTERFACE BLOCK SIGNAL ......................................................................................... 173

TABLE 6: DESCRIPTION OF THE MICROPROCESSOR INTERFACE SIGNALS THAT EXHIBIT CONSTANT ROLES IN BOTH

THE

"INTEL" AND "MOTOROLA" MODES .................................................................................... 174

TABLE 7: PIN DESCRIPTION OF MICROPROCESSOR INTERFACE SIGNALS - WHILE THE MICROPROCESSOR INTER-

FACE IS

OPERATING IN THE INTEL MODE ................................................................................... 174

TABLE 8: PIN DESCRIPTION OF THE MICROPROCESSOR INTERFACE SIGNALS WHILE THE MICROPROCESSOR IN-

TERFACE IS OPERATING IN THE

MOTOROLA MODE .................................................................... 175

3.2 INTERFACING THE XRT72L13 DS3 FRAMER TO THE LOCAL µC/µP OVER VIA THE MICROPROCESSOR INTERFACE

BLOCK

175

3.2.1 Interfacing the XRT72L13 DS3 Framer to the Microprocessor over an 8 bit wide bi-directional Data Bus

175

3.2.2 Data Access Modes ........................................................................................................................... 176

Figure 47. Behavior of Microprocessor Interface signals during an "Intel-type" Programmed I/O

Read Operation ................................................................................................................... 177

Figure 48. Behavior of the Microprocessor Interface Signals, during an "Intel-type" Programmed I/

O Write Operation ............................................................................................................... 178

Figure 49. Illustration of the Behavior of Microprocessor Interface signals, during a "Motorola-type"

Programmed I/O Read Operation ...................................................................................... 179

Figure 50. Illustration of the Behavior of the Microprocessor Interface signal, during a "Motorola-

type" Programmed I/O Write Operation ............................................................................ 180

Figure 51. Behavior of the Microprocessor Interface Signals, during the "Initial" Read Operation of

a Burst Cycle (Intel Type Processor) ................................................................................ 182

Figure 52. Behavior of the Microprocessor Interface Signals, during subsequent "Read" Operations

within the Burst I/O Cycle ................................................................................................... 183

Figure 53. Behavior of the Microprocessor Interface signals, during the "Initial" Write Operation of

a Burst Cycle (Intel-type Processor) ................................................................................. 184

Figure 54. Behavior of the Microprocessor Interface Signals, during subsequent "Write" Operations

within the Burst I/O Cycle ................................................................................................... 185

Figure 55. Behavior of the Microprocessor Interface Signals, during the "Initial" Read Operation of

a Burst Cycle (Motorola Type Processor) ......................................................................... 186

Figure 56. Behavior the Microprocessor Interface Signals, during subsequent "Read" Operations

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