LP8556 datasheet(28/63 Pages) TI1

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SDA

SCL

Data Line

Stable:

Data Valid

Change

of Data

Allowed

LP8556

SNVS871I – JULY 2012 – REVISED MARCH 2016

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8.4 Device Functional Modes

8.4.1 Shutdown Mode

The device is in shutdown mode when the EN/VDDIO input is low. Current consumption in this mode from VDD

pin is < 1.6 µA.

8.4.2 Active Mode

In active mode the backlight is enabled either with setting the ON register bit high (BRTMODE = 0 1, 10, 11) or

by activating PWM input (BRTMODE=00). The powers supplying the VDD and EN/VDDIO pins must be present.

Brightness is controlled with I2C writes to brightness registers or by changing PWM input duty cycle (operation

without I2C control). Configuration registers are not accessible in Active mode to prevent damage to the device

by accidental writes. Current consumption from VDD pin this mode is typically 2.2 mA when boost is enabled and

LEDs are not drawing any current.

8.5 Programming

8.5.1 I2C-Compatible Serial Bus Interface

8.5.1.1 Interface Bus Overview

The I2C-compatible synchronous serial interface provides access to the programmable functions and registers on

the device. This protocol uses a two-wire interface for bidirectional communications between the ICs connected

to the bus. The two interface lines are the Serial Data Line (SDA) and the Serial Clock Line (SCL). These lines

must be connected to a positive supply via a pull-up resistor and remain HIGH even when the bus is idle.

Every device on the bus is assigned a unique address and acts as either a Master or a Slave depending on

whether it generates or receives the SCL. The LP8556 can operate as an I2C slave.

8.5.1.2

Data Transactions

One data bit is transferred during each clock pulse. Data is sampled during the high state of the serial clock SCL.

Consequently, throughout the clock’s high period, the data should remain stable. Any changes on the SDA line

during the high state of the SCL and in the middle of a transaction, aborts the current transaction. New data

should be sent during the low SCL state. This protocol permits a single data line to transfer both

command/control information and data using the synchronous serial clock.

Figure 13. Bit Transfer

Each data transaction is composed of a Start Condition, a number of byte transfers (set by the software) and a

Stop Condition to terminate the transaction. Every byte written to the SDA bus must be 8 bits long and is

transferred with the most significant bit first. After each byte, an Acknowledge signal must follow. The following

sections provide further details of this process.

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