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LP5907 датащи(PDF) 17 Page - Texas Instruments |
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LP5907 датащи(HTML) 17 Page - Texas Instruments |
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17 / 36 page ![]() VIN VOUT Power Ground VEN CIN COUT LP5907SN 1 2 3 4 IN GND EN OUT N/C CIN COUT 1 2 3 4 5 VIN GND Enable VOUT GND 17 LP5907 www.ti.com SNVS798J – APRIL 2012 – REVISED MARCH 2016 Product Folder Links: LP5907 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated 10 Layout 10.1 Layout Guidelines The dynamic performance of the LP5907 is dependant on the layout of the PCB. PCB layout practices that are adequate for typical LDOs may degrade the PSRR, noise, or transient performance of the LP5907. Best performance is achieved by placing CIN and COUT on the same side of the PCB as the LP5907, and as close to the package as is practical. The ground connections for CIN and COUT must be back to the LP5907 ground pin using as wide and short a copper trace as is practical. Connections using long trace lengths, narrow trace widths, and/or connections through vias must be avoided. These add parasitic inductances and resistance that results in inferior performance especially during transient conditions 10.2 Layout Examples Figure 24. LP5907MF-x.x (SOT-23) Typical Layout Figure 25. LP5907SN-xx (X2SON) Typical Layout |
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