TUSB3210 datasheet(18/44 Pages) TI

18 / 44 page

2–6

Table 2–2. Memory Mapped Registers Summary (XDATA Range = FF80

→ FFF) (Continued)

ADDRESS

DESCRIPTION

FF91

RESERVED

FF90

MCNFG

MCNFG: MCU configuration register

↑

RESERVED

FF84

INTCFG

INTCFG: Interrupt delay configuration register

FF83

OEPBCNT_0

OEPBCNT_0: Output endpoint-0 byte count register

FF82

OEPCNFG_0

OEPCNFG_0: Output endpoint-0 configuration register

FF81

IEPBCNT_0

IEPBCNT_0: Input endpoint-0 byte count register

FF80

IEPCNFG_0

IEPCNFG_0: Input endpoint-0 configuration register

Table 2–3. EDB and Buffer Allocations in XDATA

ADDRESS

DESCRIPTION

FF7F

↑

(32–bytes)

RESERVED

(32 bytes)

RESERVED

FF60

FF5F

↑

(8–bytes)

Input endpoint_3: configuration

FF58

(8 bytes)

In ut end oint_3: configuration

FF57

↑

(8–bytes)

Input endpoint_2: configuration

FF50

(8 bytes)

In ut end oint_2: configuration

FF4F

↑

(8–bytes)

Input endpoint_1: configuration

FF48

(8 bytes)

In ut end oint_1: configuration

FF47

↑

(40–bytes)

RESERVED

FF20

FF1F

↑

(8–bytes)

Output endpoint_3: configuration

FF18

(8 bytes)

Out ut end oint_3: configuration

FF17

↑

(8–bytes)

Output endpoint_2: configuration

FF10

(8 bytes)

Out ut end oint_2: configuration

FF0F

↑

(8–bytes)

Output endpoint_1: configuration

FF08

(8 bytes)

Out ut end oint_1: configuration

FF07

↑

(8–bytes)

Setup packet block

FF00

(8 bytes)

Setu

acket block

FEFF

↑

(8–bytes)

Input endpoint_0 buffer

FEF8

(8 bytes)

In ut end oint_0 buffer

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