LM3554TMXSLASHNOPB datasheet(40/47 Pages) TI1

40 / 47 page

4.5 mm

5.1 mm

LM3554

SNVS549C – JUNE 2009 – REVISED FEBRUARY 2016

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10 Layout

10.1 Layout Guidelines

The high frequency and large switching currents of the LM3554 make the choice of layout important. Use the

following steps as a reference to ensure the device is stable and maintains proper voltage and current regulation

across its intended operating voltage and current range.

1. Place CIN on the top layer (same layer as the LM3554) and as close to the device as possible. The input

capacitor conducts the driver currents during the low-side MOSFET turnon and turnoff and can see current

spikes over 1 A in amplitude. Connecting the input capacitor through short wide traces on both the IN and

GND terminals reduces the inductive voltage spikes that occur during switching and which can corrupt the

VIN line.

2. Place COUT on the top layer (same layer as the LM3554) and as close to the OUT and GND pins as possible.

The returns for both CIN and COUT must come together at one point, and as close to the GND pin as

possible. Connecting COUT through short wide traces reduces the series inductance on the OUT and GND

pins that can corrupt the VOUT and GND lines and cause excessive noise in the device and surrounding

circuitry.

3. Connect the inductor on the top layer close to the SW pin. There must be a low impedance connection from

the inductor to SW due to the large DC inductor current, and at the same time the area occupied by the SW

node must be small to reduce the capacitive coupling of the high dV/dt present at SW that can couple into

nearby traces.

4. Avoid routing logic traces near the SW node to avoid any capacitively coupled voltages from SW onto any

high-impedance logic lines such as TX1/TORCH/GPIO1, ENVM/TX2/GPIO2, HWEN, LEDI/NTC (NTC

mode), SDA, and SCL. A good approach is to insert an inner layer GND plane underneath the SW node and

between any nearby routed traces. This creates a shield from the electric field generated at SW.

5. Terminate the flash LED cathodes directly to the GND pin of the device. If possible, route the LED returns

with a dedicated path to keep the high amplitude LED currents out the GND plane. For flash LEDs that are

routed relatively far away from the device, a good approach is to sandwich the forward and return current

paths over the top of each other on two layers. This helps reduce the inductance of the LED current paths.

6. The NTC thermistor is intended to have its return path connected to the LED cathode. This allows the

thermistor resistive divider voltage (VNTC) to trip the comparators threshold as VNTC is falling. Additionally, the

thermistor-to-LED cathode junction can have low thermal resistivity because both the LED and the thermistor

are electrically connected at GND. The drawback is that the thermistor return detects the switching currents

from the boost converter of the LM3554. Because of this, it is necessary to have a filter capacitor at the NTC

pin which terminates close to the device GND and which can conduct the switched currents to GND.

10.2 Layout Example

Figure 66. LM3554 Layout Example

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