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CD4042BC датащи(PDF) 4 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
номер детали CD4042BC
подробное описание детали  Quad Clocked D Latch
PDF  6 Pages
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производитель  NSC [National Semiconductor (TI)]
домашняя страница  http://www.national.com
Logo NSC - National Semiconductor (TI)

CD4042BC датащи(HTML) 4 Page - National Semiconductor (TI)

  CD4042BC Datasheet HTML 1Page - National Semiconductor (TI) CD4042BC Datasheet HTML 2Page - National Semiconductor (TI) CD4042BC Datasheet HTML 3Page - National Semiconductor (TI) CD4042BC Datasheet HTML 4Page - National Semiconductor (TI) CD4042BC Datasheet HTML 5Page - National Semiconductor (TI) CD4042BC Datasheet HTML 6Page - National Semiconductor (TI)  
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AC Electrical Characteristics
TA e 25 C CL e 50 pF RL e 200k Input tr e tf e 20 ns unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
tPHL tPLH
Propagation Delay Time Data In to Q
VDD e 5V
175
350
ns
VDD e 10V
75
150
ns
VDD e 15V
60
120
ns
tPHL tPLH
Propagation Delay Time Data In to Q
VDD e 5V
150
300
ns
VDD e 10V
75
150
ns
VDD e 15V
50
100
ns
tPHL tPLH
Propagation Delay Time Clock to Q
VDD e 5V
250
500
ns
VDD e 10V
100
200
ns
VDD e 15V
80
160
ns
tPHL tPLH
Propagation Delay Time Clock to Q
VDD e 5V
250
500
ns
VDD e 10V
115
230
ns
VDD e 15V
90
180
ns
tH
Minimum Hold Time
VDD e 5V
60
120
ns
VDD e 10V
30
60
ns
VDD e 15V
25
50
ns
tSU
Minimum Setup Time
VDD e 5V
0
50
ns
VDD e 10V
0
30
ns
VDD e 15V
0
25
ns
tW
Minimum Clock Pulse Width
VDD e 5V
100
200
ns
VDD e 10V
50
100
ns
VDD e 15V
30
60
ns
tTHL tTLH
Transition Time
VDD e 5V
125
250
ns
VDD e 10V
60
125
ns
VDD e 15V
50
100
ns
CIN
Input Capacitance
Any Input
50
75
pF
AC Parameters are guaranteed by DC correlated testing
Note 1
‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed They are not meant to imply that the
devices should be operated at these limits The tables of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provide conditions for actual
device operation
Note 2
VSS e 0V unless otherwise specified
Note 3
Being a latch the CD4042BMCD4042BC is not clock rise and fall time sensitive
Note 4
IOH and IOL are tested one output at a time
4



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