TLF5958

February 1988

CD4027BMCD4027BC Dual J-K MasterSlave

Flip-Flop with Set and Reset

General Description

These dual J-K flip-flops are monolithic complementary

MOS (CMOS) integrated circuits constructed with N- and P-

channel enhancement mode transistors Each flip-flop has

independent J K set reset and clock inputs and buffered

Q and Q outputs These flip-flops are edge sensitive to the

clock input and change state on the positive-going transition

of the clock pulses Set or reset is independent of the clock

and is accomplished by a high level on the respective input

All inputs are protected against damage due to static dis-

Features

Y

Wide supply voltage range

30V to 15V

Y

High noise immunity

Y

Low power TTL

Fan out of 2 driving 74L

compatibility

or 1 driving 74LS

Y

Low power

50 nW (typ)

Y

Medium speed operation

12 MHz (typ)

with 10V supply

Schematic and Connection Diagrams

TLF5958 – 1

Dual-In-Line Package

TLF5958 – 2

Top View

Order Number CD4027B

C1995 National Semiconductor Corporation

RRD-B30M105Printed in U S A