AX88796LF datasheet(34/71 Pages) ASIX

34 / 71 page

ASIX ELECTRONICS CORPORATION

AX88796 L

3-in-1 Local Bus Fast Ethernet Controller

5.1.1 Command Register (CR) Offset 00H (Read/Write)

FIELD

NAME

DESCRIPTION

7:6

PS1,PS0 PS1,PS0 : Page Select

The two bits selects which register page is to be accessed.

PS1

PS0

page 0

page 1

5:3

RD2,RD1

,RD0

RD2,RD1,RD0 : Remote DMA Command

These three encoded bits control operation of the Remote DMA channel. RD2 could be set

to abort any Remote DMA command in process. RD2 is reset by AX88796 when a Remote

DMA has been completed. The Remote Byte Count should be cleared when a Remote DMA

has been aborted. The Remote Start Address is not restored to the starting address if the

Remote DMA is aborted.

RD2

RD1

RD0

Not allowed

Remote Read

Remote Write

Not allowed

Abort / Complete Remote DMA

TXP

TXP : Transmit Packet

This bit could be set to initiate transmission of a packet

START START :

This bit is used to active AX88796 operation.

STOP

STOP : Stop AX88796

This bit is used to stop the AX88796 operation.

5.1.2 Interrupt Status Register (ISR) Offset 07H (Read/Write)

FIELD

NAME

DESCRIPTION

RST

Reset Status :

Set when AX88796 enters reset state and cleared when a start command is issued to the

CR. Writing to this bit is no effect.

RDC

Remote DMA Complete

Set when remote DMA operation has been completed

CNT

Counter Overflow

Set when MSB of one or more of the Tally Counters has been set.

OVW

OVERWRITE : Set when receive buffer ring storage resources have been exhausted.

TXE

Transmit Error

Set when packet transmitted with one or more of the following errors

n Excessive collisions

FIFO Underrun

RXE

Receive Error

Indicates that a packet was received with one or more of the following errors

CRC error

Frame Alignment Error

FIFO Overrun

Missed Packet

PTX

Packet Transmitted

Indicates packet transmitted with no error

PRX

Packet Received

Indicates packet received with no error.

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