SP3243E datasheet(8/14 Pages) SIPEX

8 / 14 page

Rev.4/08/02

SP3249E Intelligent +3.0V to +5.5V RS-232 Transceivers

— V

DD charge storage — The third phase of the

clock is identical to the first phase — the charge

transferred in C

1 produces –VCC in the negative

terminal of C

1, which is applied to the negative

side of capacitor C

Since C

+ is at V

CC, the

voltage potential across C

2 is 2 times VCC.

Phase 4 (Figure 15)

— V

DD transfer — The fourth phase of the clock

connects the negative terminal of C

2 to GND,

and transfers this positive generated voltage

across C

2 to C4, the VDD storage capacitor. This

voltage is regulated to +5.5V. At this voltage,

the internal oscillator is disabled. Simultaneous

with the transfer of the voltage to C

4, the

positive side of capacitor C

1 is switched to VCC

and the negative side is connected to GND,

allowing the charge pump cycle to begin again.

The charge pump cycle will continue as long as

the operational conditions for the internal

oscillator are present.

Since both V+ and V– are separately generated

from V

CC, in a no–load condition V

+ and V– will

be symmetrical. Older charge pump approaches

that generate V– from V+ will show a decrease in

the magnitude of V– compared to V+ due to the

inherent inefficiencies in the design.

The clock rate for the charge pump typically

operates at 500kHz. The external capacitors can

be as low as 0.1

µF with a 16V breakdown

voltage rating.

Figure 11. Charge Pump — Phase 2

VCC = +5V

–10V

VSS Storage Capacitor

VDD Storage Capacitor

–

VCC = +5V

–5V

+5V

VSS Storage Capacitor

VDD Storage Capacitor

–

Figure 10. Charge Pump — Phase 1

Figure 12. Charge Pump Waveforms

Ch1 2.00V Ch2 2.00V M 1.00

µs Ch1 1.96V

[]

+6V

a) C2+

b) C2-

-6V

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