SL11RIDE
Document #: 38-08007 Rev. **
Page 23 of 27
A4
38
Output
External Memory Address Bus, A4
A3
39
Output
External Memory Address Bus, A3
GND
40
GND
Digital ground
A2
41
Output
External Memory Address Bus, A2
A1
42
Output
External Memory Address Bus, A1
A0
43
Output
External Memory Address Bus, A0
TEST
44
Input
No Connection, MFG test only
nWRL
45
Output
Active LOW, Write to lower bank of External SRAM
nWRH
46
Output
Active LOW, Write to upper bank of External SRAM
nRD
47
Output
Active LOW, Read from External SRAM or ROM
nRESET
48
Input
Master Reset. SL11R Device active low reset input.
nRAS
49
Output
Active LOW, DRAM Row Address Select
VDD
50
Power
+3.3 VDC Supply
VDD
51
Power
+3.3 VDC Supply
nCASL
52
Output
Active LOW, DRAM Column Low Address Select
nCASH
53
Output
Active LOW, DRAM Column High Address Select
nDRAMOE
54
Output
Active LOW, DRAM Output Enable
nDRAMWR
55
Output
Active LOW, DRAM Write
nXRAMSEL
56
Output
Active LOW, select external SRAM (16 bit)
nXROMSEL
57
Output
Active LOW, select external ROM
nXMEMSEL
58
Output
Active LOW, select external Memory bus, external SRAM, DRAM, ROM
or any memory mapped device
X_PCLK
59
Bidir
See register 0xC006 for more information
SECLK
60
GPIO31
Bidir
SECLK, Serial EEPROM clock, or GPIO31
SEDO
61
GPIO30
Bidir
SEDO, Serial flash EPROM Data, or GPIO30
This pin requires a 5-k
Ω pull-up.
GPIO29
62
GPIO29
Bidir
GPIO29
UART_TXD
63
GPIO28
Output
UART Transmit Data (out), or GPIO28
GND
64
GND
Digital ground
GND
65
GND
Digital ground
UART_RXD
66
GPIO27
Input
UART Receive Data (in), or GPIO27
nENS
67
GPIO26
Output
Serial EPROM control signal
CLKS
68
GPIO25
Output
Serial EPROM Clock
nDTSRB
69
GPIO24
Output
EPP Data Strobe
nASTRB
70
GPIO23
Output
EPP Address Strobe
nWRITE
71
GPIO22
Output
EPP Write Strobe
P9
72
GPIO21
Output
P Register
P5
73
GPIO20
Output
P Register or PWR_OFF
P4
74
GPIO19
Output
P Register
Table 10-5. Fast EPP Pin Assignment and Description (continued)
Pin Name
Pin No.
GPIO Pins
Pin Type
GPIO & Fast EPP Pin Chip Revision 1.1
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