Silicon Image, Inc.

SiI 150A

SiI/DS-0006-C

Revision C

5

Subject to Change without Notice

Configuration Pin Description

Pin Name

Pin #

Type

Description

EDGE

24

In

Data/Control Latching Edge. A low level indicates that all input signals (DIE/DIO[23:0], HSYNC, VSYNC, DE,

and CTL[3:1]) are latched on the falling edge of IDCK, while a high level (3.3V) indicates that all input signals

are latched on the rising edge of IDCK.

PIXS

25

In

Pixel Select. A low level indicates one pixel (up to 24-bits) per clock mode using DIE[23:0]. A high level

(3.3V) indicates two pixels (up to 48-bits) per clock mode using DIE[23:0] for the first pixel and DIO[23:0] for

the second pixel.

Power Management Pin Description

Pin Name

Pin #

Type

Description

PD

26

In

Power Down (active low). A high level (3.3V) indicates normal operation and a low level (GND) indicates

power down mode. During power down mode, all data (DIE/DIO[23:0]), data enable (DE), clock (IDCK) and

control signals (HSYNC, VSYNC, CTL[3:1]), input buffers are disabled, all output buffers are tri-stated, and all

internal circuitry is powered down.

Differential Signal Data Pin Description

Pin Name

Pin #

Type

Description

TX0+

TX0-

TX1+

TX1-

TX2+

TX2-

40

39

43

42

46

45

Analog

Analog

Analog

Analog

Analog

Analog

TMDS Low Voltage Differential Signal output data pairs.

TXC+

TXC-

35

34

Analog

Analog

TMDS Low Voltage Differential Signal output data pairs.

EXT_SWING

32

Analog

Voltage Swing Adjust. A resistor should tie this pin to AVCC. The amplitude of the voltage swing is

determined by this resistance. For remote display applications, 510

Ω is recommended. For notebook

computers, 680

Ω is recommended.

Reserved Pin Description

Pin Name

Pin #

Type

Description

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

20

21

22

23

27

28

29

87

In

In

In

In

In

In

In

In

Reserved for future use. Must be tied HIGH for normal operation.

Reserved for future use. Must be tied LOW for normal operation.

Reserved for future use. Must be tied HIGH for normal operation.

Reserved for future use. Must be tied HIGH for normal operation.

Reserved for future use. Must be tied HIGH for normal operation.

Reserved for future use. Must be tied HIGH for normal operation.

Reserved for future use. Must be tied HIGH for normal operation.

Reserved for future use. Must be tied HIGH for normal operation.

Power and Ground Pin Description

Pin Name

Pin #

Type

Description

VCC

8,30,56,88

Power

Digital Core VCC, must be set to 3.3V.

GND

7,31,57,67,79,89

Ground

Digital GND.

IVCC

17,66,81,98

Power

Input VCC, must be set to 3.3V.

AVCC

36,38,44

Power

Analog VCC, must be set to 3.3V.

AGND

33,37,41,47

Ground

Analog GND.

PVCC1

18

Power

PLL Analog VCC, must be set to 3.3V.

PVCC2

85

Power

PLL Analog VCC, must be set to 3.3V.

PGND1

19

Ground

PLL Analog GND. PGND1 should not be directly connected to PGND2 before being

connected to the GROUND plane. They should be connected individually to the GROUND

plane.

PGND2

86

Ground

PLL Analog GND. PGND1 should not be directly connected to PGND2 before being

connected to the GROUND plane. They should be connected individually to the GROUND

plane.

Application Information

To obtain the most updated Application Notes and other useful information for your design application, please visit the Silicon Image

web site at www.siimage.com, or contact your local Silicon Image sales office.