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INTRODUCTION

The UT64BS1X433 64-Channel 1:4 Bus Switch is built on a 0.35

μm Triple-Well CMOS process. The device incorporates control

logic that electrically connects input bank A to the output banks B0-B3, depending upon the selected channel. The control logic also

decodes the address pins to provide chip-select outputs to up to 32 discrete memory devices. To ensure that important memory con-

trol lines e.g. RD and WR are consistently driven, regardless of the switching logic, the Matrix-A provides two 2-to-4 fanout buf-

fers. Typical applications will connect the processor or memory controller’s RD and WR output signals to XIN and YIN on the

Matrix-A, and tie the corresponding XOUTn and YOUTn to the RD and WR memory inputs on each bank.

Figure 1. UT64BS1X433 Functional Block Diagram

Channel Select

Decoder Logic

0A

63A

MODE

RAMS

ROMS

ASEL[2:0]

BSEL[2:0]

BANK[1:0]

0B0

0B1

0B2

0B3

63B0

63B1

63B2

63B3

CS3[7:0]

CS2[7:0]

CS1[7:0]

CS0[7:0]

XIN[0]

YIN[0]

XOUT0

XOUT1

XOUT2

XOUT3

YOUT0

YOUT1

YOUT2

YOUT3

S

S

S

S

S

S

S

S

XIN[1]

YIN[1]

36-00-03-001

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