OBSOLETE

CLC412

www.ti.com

SNOS833D – AUGUST 2000 – REVISED APRIL 2013

Circuit Layout

With all high frequency devices, board layouts with stray capacitances have a strong influence over AC

performance. The CLC412 is no exception and its input and output pins are particularly sensitive to the coupling

of parasitic capacitances (to AC ground) arising from traces or pads placed too closely (<0.1”) to power or

ground planes. In some cases, due to the frequency response peaking caused by these parasitics, a small

adjustment of the feedback resistor value will serve to compensate the frequency response. Also, it is very

important to keep the parasitic capacitance across the feedback resistor to an absolute minimum.

The performance plots in the data sheet can be reproduced using the evaluation boards available from Texas

Instruments. There are two types of boards; the PDIP (#730038) and SOIC (#730036). The #730036 board uses

all SMT parts for the evaluation of the CLC412 in its surface mount package. Either of these layouts can assist

the designer in obtaining the desired performance. In addition, the boards can serve as an example layout for the

final production printed circuit board.

Care must also be taken with the CLC412's layout in order to achieve the best circuit performance, particularly

channel-to-channel isolation. The decoupling capacitors (both tantalum and ceramic) must be chosen with good

high frequency characteristics to decouple the power supplies and the physical placement of the CLC412's

external components is critical. Grouping each amplifier's external components with their own ground connection

and separating them from the external components of the opposing channel with the maximum possible distance

the ceramic decoupling capacitor (0.1µF chip or radial-leaded with low ESR) should be placed as closely to the

power pins as possible.

Package Parasitics

In addition to the parasitic capacitances arising from the board layout, each of the CLC412's packages has its

own characteristic set of parasitic capacitances and inductances causing frequency response variation from

package to package as shown in the plot below (Figure 37), labeled “Frequency Response vs. Package Type”.

Due to its much smaller size, the CLC412AJE (8-pin SOIC) shows the least amount of peaking.

Figure 37. Frequency Response vs. Package Type

Matching Performance

With proper board layout, the AC performance match between the two CLC412's amplifiers can be tightly

controlled as shown in TYPICAL PERFORMANCE CHARACTERISTICS plot labeled “Small-Signal Channel

Matching”.

Copyright © 2000–2013, Texas Instruments Incorporated

Submit Documentation Feedback

13

Product Folder Links: CLC412