ISL95901

4

FN7893.1

January 22, 2015

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15, 16, 17

VIN1

Input supply for power stage of SMPS1 regulator and source for internal linear regulator, LDO. For

decoupling, place a minimum of 10µF ceramic capacitance from VIN1 to PGND1 and close to IC.

19, 23, 29, 30,

PAD3

PHASE2

Switch node output of channel 2. Connects source of internal power MOSFETs with external output inductor.

Connect exposed PAD3 as close to inductor of SMPS2 as possible.

20, 21, 22

VIN2

Input supply for power stage of SMPS2 regulator. For decoupling, place a minimum of 10µF ceramic

capacitance from VIN2 to PGND2 and close to the IC.

24, 25, 26, 27,

28

PGND2

Power ground of SMPS2.

31

BOOT2

Floating bootstrap supply pin for power MOSFET gate driver. Bootstrap capacitor provides necessary charge

to turn on high-side internal N-channel MOSFET of channel 2. Connect an external capacitor from this pin to

PHASE2.

32

EN2

SMPS2 controller enable input. PWM controller is held off when pin is pulled to ground. When voltage on

this pin rises above 1.4V, PWM controller is enabled.

34

FB2

SMPS2 feedback Input. Connect FB2 to a resistive voltage divider from SVIN2 to GND2 to adjust the output

from 0.8V to 5.5V.

35

VSIN2

Sensing for output of SMPS2. Must be connected to channel 2 output side of inductor.

36

STB2

Standby output 2 enable input. Standby output 2 is held off when pin is pulled to ground. When voltage on

this pin rises above 1.4V, standby output 2 controller is enabled.

37

PG2

Open drain power-good of SMPS2. Pulled to ground when output voltage is below regulation limits or during

soft-start interval. Contains an internal 5MΩ pull-up resistor.

38

VSOUT2

Standby output 2. There is a switch between VSIN2 and VSOUT2.

39

BYP5

Connect BYP5 to 5V buck output or external 5V source, this will allow IC to disable VCC and LDO5, then the

power source will be drawn from BYP5 to minimize internal power dissipation. Tie to GND if not use.

40

VCC

Voltage bias for gate drivers as well as all other control circuitries. Power on or off by VIN. Decouple with at

least 1µF of an MLCC capacitor across VCC and PAD1.

41

VIN

Input LDO3P3, LDO5 and VCC. For decoupling, place a minimum of 1µF ceramic capacitance close to IC.

42

LDO5

5V linear regulator output. Power on or off by VIN. Can provide a total of 100mA external loads. Bypass

LDO5 output with a minimum of 4.7µF ceramic.

43

BYP3P3

Connect BYP3P3 to 3.3V buck output or external 3.3V source, this will allow IC to disable LDO3P3, then the

power source will be drawn from BYP3P3 to minimize internal power dissipation. Tie to GND if not used.

44

MODE

Mode selection pin. Connect to logic high or VCC for PWM mode. Connect to logic low or ground for DCM

mode. An internal 5MΩ pull-down resistor prevents undefined logic state in case of MODE pin float.

45

LDO3P3

3.3V linear regulator output. Power on or off by VIN. Can provide a total of 100mA external loads. Bypass

LDO3P3 output with a minimum of 4.7µF ceramic.

46

PG1

Open drain power-good of SMPS1. Pulled to ground when output voltage is below regulation limits or during

soft-start interval. Contains an internal 5MΩ pull-up resistor.

PIN NUMBER

SYMBOL

PIN DESCRIPTION

Ordering Information

PART NUMBER

(Notes 1, 2, 3)

PART

MARKING

TEMP. RANGE

(°C)

PACKAGE

(RoHS Compliant)

PKG.

DWG. #

ISL95901IRZ

95901 IRZ

-40 to +85

46 Ld QFN

L46.5x6

ISL95901EVAL1Z

Evaluation Board

NOTES:

1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.

2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials and 100% matte tin

plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free

products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

3. For Moisture Sensitivity Level (MSL), please see device information page for ISL95901. For more information on MSL please see Tech Brief TB363.