Aeroflex Colorado Springs Application Note

AN-MEM-002

Creation Date: 8/19/11

Page 5 of 5

Modification Date: 4/24/13

4.0 Summary and Conclusion

The Aeroflex SRAMs in Table #1 all employ a low power consumption read architecture. Power is conserved by sensing data

only when new data is requested. A request occurs anytime chip enable is asserted or any address input signal transitions while

chip enable is asserted. The data sheets for the SRAMs listed in Table #1 do not explicitly define the case of simultaneous

switching of address and control signals during read operations. Data sheet read cycle descriptions indicate that control inputs

are established prior to address changes, and address inputs are stable prior to control assertions. Simultaneous switching of

addresses and controls is tolerable, when the skew between all input signals is < 4ns. For designs that must employ the simul-

taneous activation of address and control signals, two important issues should be considered by the designer. The first is the

input signal skew sensitivity of the low power read architecture discussed by this application note. The second is the instanta-

neous current consumption that results from simultaneous access methods. Aeroflex recommends the use of only one read

access method at a time. If multiple read accesses (simultaneous chip enable assertion and address switching) cannot be

avoided, then Aeroflex recommends that the chip enable signal be delayed until all addresses have completed transitions.