Future Technology Devices Intl.

FT8U232AM Preliminary Information Rev 0.8 – Subject to Change

FT8U232AM - FUNCTIONAL BLOCK DESCRIPTION

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3.3V LDO Regulator

The 3.3V LDO Regulator generates the 3.3 volt reference voltage for driving the USB transceiver cell

output buffers. It requires an external decoupling capacitor to be attached to the 3V3OUT regulator

output pin.

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USB Transceiver

The USB Transceiver Cell provides the USB 1.1 full-speed physical interface to the USB cable. The

output drivers provide 3.3 volt level slew rate control signalling, whilst a differential receiver and two single

ended receivers provide USB data in, SEO and USB Reset condition detection.

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USB DPLL

The USB DPLL cell locks on to the incoming NRZI USB data and provides separate recovered clock and

data signals to the SIE block.

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6MHz Oscillator

The 6MHz Oscillator cell generates a 6MHz reference clock input to the X8 Clock multiplier from an

external 6MHz crystal or ceramic resonator.

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X8 Clock Multiplier

The X8 Clock Multiplier takes the 6MHz input from the Oscillator cell and generates a 12MHz reference

clock for the SIE, USB Protocol Engine and UART FIFO controller blocks. It also generates a 48MHz

reference clock for the USB DPPL and the Baud Rate Generator blocks.

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Serial Interface Engine ( SIE )

The Serial Interface Engine ( SIE ) block performs the Parallel to Serial and Serial to Parallel conversion

of the USB data. In accordance to the USB 1.1 specification, it performs bit stuffing / un-stuffing and

CRC5 / CRC16 generation / checking on the USB data stream.

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USB Protocol Engine

The USB Protocol Engine manages the data stream from the device USB control endpoint. It handles the

low level USB protocol ( Chapter 9 ) requests generated by the USB host controller and the commands

for controlling the functional parameters of the UART.

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Dual Port TX Buffer ( 128 bytes )

Data from the USB data out endpoint is stored in the Dual Port TX buffer and removed from the buffer to

the UART transmit register under control of the UART FIFO controller.