TLE6285 datasheet(8/23 Pages) INFINEON

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Target Data

TLE 6285

Version 1.02

2002-05-15

very short, the VLD level is not reached and no reset-signal is asserted. This feature

avoids resets at short negative spikes at the output voltage e.g. caused by load changes.

As soon as the output voltage is more positive than the reset threshold, the delay

capacitor is charged with constant current. When the voltage reaches VUD the reset

output RO is set High again.

The reset threshold is either the internal defined VRT voltage (typical 4.6 V) or can be

lowered by a voltage level at the RTh input down to 3.5 V. The reset delay time and the

reset reaction time are defined by the external capacitor CD. The reset function is active

down to VI = 1 V.

The device is capable to supply 150 mA. For protection at high input voltage above 25 V,

the output current is reduced (SOA protection).

2.5

Reset

The power on reset feature is necessary for a defined start of the microprocessor when

switching on the application. For the reset delay time after the output voltage of the

regulator is above the reset threshold, the reset signal is set High again. The reset delay

time is defined by the reset delay capacitor CD at pin RD (refer to figure 4 and 5).

The under-voltage reset circuitry supervises the output voltage. In case VQ decreases

below the reset threshold the reset output is set LOW after the reset reaction time. The

reset LOW signal is generated down to an output voltage VCC to 1 V. Both the reset

reaction time and the reset delay time is defined by the capacitor value.

The power on reset delay time is defined by the charging time of an external delay

capacitor CD.

CD = (td ´ ID) / DV

[1]

With

reset delay capacitor

reset delay time

VUD,

typical 1.8 V for power up reset

VUD – VLD typical 1.35 V for undervoltage reset

charge current typical 6.5

For a delay capacitor CD =100 nF the typical power on reset delay time is 28 ms.

The reset reaction time tRR is the time it takes the voltage regulator to set reset output

LOW after the output voltage has dropped below the reset threshold. It is typically 1

for delay capacitor of 100 nF. For other values for CD the reaction time can be estimated

using the following equation:

tRR = 10 ns / nF ´ CD

[2]

The reset output is an open collector output with a pull-up resistor of typical 20 k

W to Q.

An external pull-up can be added with a resistor value of at least 5.6 k

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