TLE6263 datasheet(14/40 Pages) INFINEON

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Final Datasheet TLE 6263

Version 2.08

2004-06-07

period a watchdog trigger is detected as a “rising edge” by sampling a HIGH on the IBIT

0. The trigger is accepted when the CSN input becomes HIGH after the transmission of

the SPI word. After each reset as well as after a power on condition the default value of

IBIT 0 is LOW.

Closed and Open Window

A correct watchdog trigger results in starting the window watchdog by opening a closed

window of typ. 6 ms followed by a open window of typ. 10 ms. From now on the

microcontroller has to service the watchdog trigger by inverting the IBIT 0 alternating.

The “negative” or “positive” edge has to meet the open window time. A correct watchdog

service immediately results in starting the next closed window. Please refer to figure 12,

Watchdog Timing Diagram.

Watchdog Reset

Should the trigger signal not meet the open window a watchdog reset is created by

setting the reset output RO low for a period of typ. 2 ms. Then the watchdog starts again

by opening a long open window. In addition, the SPI OBIT 1 (diagnosis bit 1) is set HIGH

until the next successful watchdog trigger to monitor a watchdog reset. OBIT1 is also

HIGH until the watchdog is correctly triggered after power-up / start-up. For fail safe

reasons the TLE6263 is automatically switched in Vbat-stand-by mode if a watchdog

trigger failure occurs. So the power consumption can be minimized in case of a

permanent faulty microcontroller.

In case of either an undervoltage reset or a watchdog reset all SPI input registers (IBIT

0 to IBIT 7) are set low.

Undercurrent Disabling Function

To avoid cyclic wake-up’s of the microcontroller due to missing watchdog pulses when

the microcontroller is in a low power mode, an automatic undercurrent disabling function

of the watchdog circuit can be selected for the TLE 6263 Vbat-stand-by mode. For

activation of this feature, the VCC output current in the Vbat-stand-by mode has to be less

than the undercurrent threshold (ICC < ICCWD) and in addition the SPI IBIT 7 has to be

set HIGH. When the microcontroller returns back to normal mode or the output current

becomes higher than ICC > ICCWD the watchdog circuit is enabled again. A long open

window is started then, to ensure a simple synchronization of the watchdog timing to the

watchdog services of the microcontroller.

6.7

Flash program mode

To disable the watchdog feature a flash program mode is available. This mode is

selected by applying a voltage of 6.8V < VINT < 7.2V at pin INT. This is useful e.g. if the

flash-memory of the micro has to be programmed and therefore a regular watchdog

triggering is not possible. If the SPI is required in the flash program mode to change e.g.

the mode of the TLE6263 the first input telegram has to be “00000000”.

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