1

Standard Products

UT54ACS86/UT54ACTS86

Quadruple 2-Input Exclusive OR Gates

Datasheet

November 2010

www.aeroflex.com/logic

FEATURES

1.2μ CMOS

- Latchup immune

High speed

Low power consumption

Single 5 volt supply

Available QML Q or V processes

Flexible package

- 14-pin DIP

- 14-lead flatpack

UT54ACS86 - SMD 5962-96538

UT54ACTS86 - SMD 5962-96539

DESCRIPTION

The UT54ACS86 and the UT54ACTS86 are quadruple 2-input

exclusive OR gates. The devices perform the Boolean function

Y = A

⊕B = AB + AB in positive logic.

An application is as a true/complement element. If one of the

inputs is low, the other input will be reproduced in true form at

the output. If one of the inputs is high, the signal on the other

input will be reproduced inverted at the output.

The devices are characterized over full military temperature

range of -55

°C to +125°C.

FUNCTION TABLE

LOGIC SYMBOL

PINOUTS

14-Pin DIP

Top View

14-Lead Flatpack

Top View

LOGIC DIAGRAM

INPUTS

OUTPUT

A

B

Y

L

L

L

L

H

H

H

L

H

H

H

L

Y1

(3)

(6)

Y2

Y3

(8)

(11)

Y4

(1)

A1

(2)

B1

(4)

A2

(5)

B2

(9)

A3

(10)

B3

(12)

A4

(13)

B4

Note:

1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC

Publication 617-12.

=1

A1

B1

Y1

A2

B2

Y2

B4

A4

Y4

B3

A3

Y3

114

213

312

411

510

69

78

B4

A4

Y4

B3

A3

Y3

A1

B1

Y1

A2

B2

Y2

114

213

312

411

510

69

78

B4

A4

Y4

B3

A3

Y3

B2

A2

Y2

B1

A1

Y1