1

Standard Products

UT54ACS74/UT54ACTS74

Dual D Flip-Flops with Clear & Preset

Datasheet

November 2010

www.aeroflex.com/logic

FEATURES

1.2μ CMOS

- Latchup immune

High speed

Low power consumption

Single 5 volt supply

Available QML Q or V processes

Flexible package

- 14-pin DIP

- 14-lead flatpack

UT54ACS74 - SMD 5962-96534

UT54ACTS74 - SMD 5962-96535

DESCRIPTION

The UT54ACS74 and the UT54ACTS74 contain two indepen-

dent D-type positive triggered flip-flops. A low level at the

Preset or Clear inputs sets or resets the outputs regardless of the

levels of the other inputs. When Preset and Clear are inactive

(high), data at the D input meeting the setup time requirement

is transferred to the outputs on the positive-going edge of the

clock pulse. Following the hold time interval, data at the D

input may be changed without affecting the levels at the outputs.

The devices are characterized over full military temperature

range of -55

°C to +125°C.

FUNCTION TABLE

Note:

1. The output levels in this configuration are not guaranteed to meet the minimum

addition, this configuration is nonstable; that is, it will not persist when either

preset or clear returns to its inactive (high) level.

PINOUTS

14-Pin DIP

Top View

14-Lead Flatpack

Top View

LOGIC SYMBOL

INPUTS

OUTPUT

PRE

CLR

CLK

D

Q

Q

L

H

X

X

H

L

H

L

X

X

L

H

L

L

X

X

H

H

↑

H

H

L

H

H

↑

L

L

H

H

H

L

X

1

2

3

4

5

7

6

14

13

12

11

10

8

9

CLR1

D1

CLK1

PRE1

Q1

Q1

CLR2

D2

CLK2

PRE2

Q2

Q2

1

2

3

4

5

7

6

14

13

12

11

10

8

9

CLR2

D2

CLK2

PRE2

Q2

Q2

CLR1

D1

CLK1

PRE1

Q1

Q1

Q1

(5)

(6)

Q1

Q2

(9)

(8)

Q2

(4)

PRE1

(3)

CLK1

(2)

D1

(1)

CLR1

(10)

PRE2

(11)

CLK2

(12)

D2

(13)

CLR2

Note:

1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC

Publication 617-12.

S

C1

D1

R